參數(shù)資料
型號： IDT82V3010
廠商： Integrated Device Technology, Inc.
英文描述： T1/E1/OC3 TELECOM CLOCK GENERATOR WITH DUAL REFERENCE INPUTS
中文描述： T1/E1/OC3電信時鐘發(fā)生器，雙基準輸入
文件頁數(shù)： 1/31頁
文件大小： 355K
代理商： IDT82V3010
IDT and IDT logo are trademarks of Integrated Device Technology, Inc.
2006 Integrated Device Technology, Inc.
DSC-6777/2
1
June 19, 2006
T1/E1/OC3 TELECOM CLOCK GENERATOR
WITH DUAL REFERENCE INPUTS
IDT82V3010
FEATURES
Supports AT&T TR62411
Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing
for E1 interface
Selectable reference inputs: 8 kHz, 1.544 MHz, 2.048 MHz or
19.44 MHz
Accepts two independent reference inputs which may have
same or different nominal frequencies applied to them
Provides C1.5o,
C3o
, C2o,
C4o
, C6o, C8o,
C16o
, C19o and
C32o
output clock signals
Provides 7 types of 8 kHz framing pulses:
F0o
, F8o,
F16o
, F19o,
F32o
, RSP and TSP
Provides a C2/C1.5 output clock signal with the frequency
controlled by the selected reference input Fref0 or Fref1
Phase slope of 5 ns per 125 μs
Attenuates wander from 2.1 Hz
Fast lock mode
Provides Time Interval Error (TIE) correction
MTIE of 1 μs
JTAG boundary scan
Holdover status indication
Freerun status indication
Normal status indication
Lock status indication
Input reference quality indication
3.3 V operation with 5 V tolerant I/O
Package: 56-pin SSOP (Green option available)
FUNCTIONAL BLOCK DIAGRAM
OSC
Reference Input
Switch
TIE Control
Block
Reference Input
Monitor 0
OSCi
TCLR
V
DDD
V
SS
V
SS
C16o
C8o
C4o
C2o
C3o
C1.5o
C6o
F0o
F8o
F16o
F19o
F32o
RSP
TSP
LOCK
F0_sel0
F0_sel1
Freerun
Normal Holdover
TDO
TDI
MON_out0
Fref1
Fref0
IN_sel
Virtual
Reference
FLOCK
Invalid Input
Signal Detection
JTAG
MODE_sel0
MODE_sel1
TIE_en
TMS
TRST
TCK
V
DDD
V
SS
V
DDD
V
DDA
V
SS
RST
Feedback Signal
State Control Circuit
Reference Input
Monitor 1
MON_out1
C19POS
C19NEG
Frequency
Select Circuit 0
Frequency
Select Circuit 1
F1_sel0
F1_sel1
C32o
C19o
DPLL
C2/C1.5
V
DDA
V
SS
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IDT82V3011PV 制造商:INT_DEV_TECH 功能描述:
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