參數(shù)資料
型號： IDT82V3255TF
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 通信及網(wǎng)絡(luò)
英文描述： WAN PLL
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP64
封裝： TQFP-64
文件頁數(shù)： 49/127頁
文件大?。?/td> 868K
代理商： IDT82V3255TF
IDT82V3255
WAN PLL
Programming Information
49
June 19, 2006
41
IN_FREQ_READ_CH_CNFG - Input
Clock Frequency Read Channel
Selection
IN_FREQ_READ_STS - Input Clock
Frequency Read Value
-
-
-
-
IN_FREQ_READ_CH[3:0]
P 79
42
IN_FREQ_VALUE[7:0]
P 80
44
IN1_IN2_CMOS_STS - CMOS Input
Clock 1 & 2 Status
-
IN2_CMOS
_FREQ_H
ARD_ALA
RM
IN2_DIFF_
FREQ_HA
RD_ALAR
M
IN2_CMOS
_NO_ACTI
VITY_ALA
RM
IN2_DIFF_
NO_ACTIV
ITY_ALAR
M
IN2_CMOS
_PH_LOC
K_ALARM
-
IN1_CMOS
_FREQ_H
ARD_ALA
RM
IN1_DIFF_
FREQ_HA
RD_ALAR
M
IN3_CMOS
_FREQ_H
ARD_ALA
RM
IN1_CMOS
_NO_ACTI
VITY_ALA
RM
IN1_DIFF_
NO_ACTIV
ITY_ALAR
M
IN3_CMOS
_NO_ACTI
VITY_ALA
RM
IN1_CMOS
_PH_LOC
K_ALARM
P 81
45
IN1_IN2_DIFF_STS - Differential Input
Clock 1 & 2 Status
-
IN2_DIFF_
PH_LOCK
_ALARM
-
IN1_DIFF_
PH_LOCK
_ALARM
P 82
47
IN3_CMOS_STS - CMOS Input Clock
3 Status
-
-
-
-
-
IN3_CMOS
_PH_LOC
K_ALARM
P 83
T0 / T4 DPLL Input Clock Selection Registers
4A
INPUT_VALID1_STS - Input Clocks
Validity 1
INPUT_VALID2_STS - Input Clocks
Validity 2
PRIORITY_TABLE1_STS - Priority
Status 1 *
PRIORITY_TABLE2_STS - Priority
Status 2 *
T0_INPUT_SEL_CNFG - T0 Selected
Input Clock Configuration
T4_INPUT_SEL_CNFG - T4 Selected
Input Clock Configuration
-
-
IN2_DIFF
IN1_DIFF IN2_CMOS IN1_CMOS
-
-
P 84
4B
-
-
-
-
-
-
-
IN3_CMOS
P 84
4E
HIGHEST_PRIORITY_VALIDATED[3:0]
CURRENTLY_SELECTED_INPUT[3:0]
P 85
4F
THIRD_HIGHEST_PRIORITY_VALIDATED[3:0]
SECOND_HIGHEST_PRIORITY_VALIDATED[3:0
]
P 86
50
-
-
-
-
T0_INPUT_SEL[3:0]
P 86
51
-
T4_LOCK_
T0
T0_FOR_T
4
T4_TEST_
T0_PH
T4_INPUT_SEL[3:0]
P 87
T0 / T4 DPLL State Machine Control Registers
EX_SYNC
_ALARM_
MON
Q_ALARM
52
OPERATING_STS - DPLL Operating
Status
T4_DPLL_
LOCK
T0_DPLL_
SOFT_FRE
T4_DPLL_
SOFT_FRE
Q_ALRAM
T0_DPLL_
LOCK
T0_DPLL_OPERATING_MODE[2:0]
P 88
53
T0_OPERATING_MODE_CNFG - T0
DPLL Operating Mode Configuration
T4_OPERATING_MODE_CNFG - T4
DPLL Operating Mode Configuration
-
-
-
-
-
T0_OPERATING_MODE[2:0]
P 89
54
-
-
-
-
-
T4_OPERATING_MODE[2:0]
P 89
T0 / T4 DPLL & APLL Configuration Registers
55
T0_DPLL_APLL_PATH_CNFG - T0
DPLL & APLL Path Configuration
T0_DPLL_START_BW_DAMPING_C
NFG - T0 DPLL Start Bandwidth &
Damping Factor Configuration
T0_DPLL_ACQ_BW_DAMPING_CNF
G - T0 DPLL Acquisition Bandwidth &
Damping Factor Configuration
T0_DPLL_LOCKED_BW_DAMPING_
CNFG - T0 DPLL Locked Bandwidth &
Damping Factor Configuration
T0_APLL_PATH[3:0]
T0_GSM_OBSAI_16E1
_16T1_SEL[1:0]
T0_12E1_24T1_E3_T3
_SEL[1:0]
P 90
56
T0_DPLL_START_DAMPING[2:0]
T0_DPLL_START_BW[4:0]
P 91
57
T0_DPLL_ACQ_DAMPING[2:0]
T0_DPLL_ACQ_BW[4:0]
P 92
58
T0_DPLL_LOCKED_DAMPING[2:0]
T0_DPLL_LOCKED_BW[4:0]
P 93
Table 34: Register List and Map (Continued)
Address
(Hex)
Register Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reference
Page
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PDF描述
IDT82V3255TFG WAN PLL
IDT82V3280 WAN PLL
IDT82V3280DQ WAN PLL
IDT82V3280DQG WAN PLL
IDT82V3280PF WAN PLL
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT82V3255TFBLANK 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL
IDT82V3255TFG 功能描述:IC PLL WAN SMC STRATUM 3 64-TQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT
IDT82V3255TFG8 功能描述:IC PLL WAN SMC STRATUM 3 64-TQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT
IDT82V3255TFGBLANK 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL
IDT82V3280 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL
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