參數(shù)資料
型號(hào): IDT82V3255TF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 通信及網(wǎng)絡(luò)
英文描述: WAN PLL
中文描述: SPECIALTY TELECOM CIRCUIT, PQFP64
封裝: TQFP-64
文件頁數(shù): 86/127頁
文件大?。?/td> 868K
代理商: IDT82V3255TF
IDT82V3255
WAN PLL
Programming Information
86
June 19, 2006
PRIORITY_TABLE2_STS - Priority Status 2 *
T0_INPUT_SEL_CNFG - T0 Selected Input Clock Configuration
Address: 4FH
Type: Read
Default Value: 00000000
Bit
Name
Description
7 - 4
THIRD_HIGHEST_PRIORITY_VALIDATED[3:0]
These bits indicate a qualified input clock with the third highest priority.
0000: No input clock is qualified. (default)
0001, 0010: Reserved.
0011: IN1_CMOS.
0100: IN2_CMOS.
0101: IN1_DIFF.
0110: IN2_DIFF.
0111, 1000: Reserved.
1001: IN3_CMOS.
1010 ~ 1111: Reserved.
These bits indicate a qualified input clock with the second highest priority.
0000: No input clock is qualified. (default)
0001, 0010: Reserved.
0011: IN1_CMOS.
0100: IN2_CMOS.
0101: IN1_DIFF.
0110: IN2_DIFF.
0111, 1000: Reserved.
1001: IN3_CMOS.
1010 ~ 1111: Reserved.
3 - 0
SECOND_HIGHEST_PRIORITY_VALIDATED[3:0]
Address: 50H
Type: Read / Write
Default Value: XXXX0000
Bit
Name
Description
7 - 4
-
Reserved.
This bit determines T0 input clock selection. It is valid only when the EXT_SW bit (b4, 0BH) is ‘0’.
0000: Automatic selection. (default)
0001, 0010: Reserved.
0011: Forced selection - IN1_CMOS is selected.
0100: Forced selection - IN2_CMOS is selected.
0101: Forced selection - IN1_DIFF is selected.
0110: Forced selection - IN2_DIFF is selected.
0111, 1000: Reserved.
1001: Forced selection - IN3_CMOS is selected.
1010 ~ 1111: Reserved.
3 - 0
T0_INPUT_SEL[3:0]
7
6
5
4
3
2
1
0
THIRD_HIGHE
ST_PRIORITY_
VALIDATED3
THIRD_HIGHE
ST_PRIORITY_
VALIDATED2
THIRD_HIGHE
ST_PRIORITY_
VALIDATED1
THIRD_HIGHE
ST_PRIORITY_
VALIDATED0
SECOND_HIGH
EST_PRIORITY
_VALIDATED3
SECOND_HIGH
EST_PRIORITY
_VALIDATED2
SECOND_HIGH
EST_PRIORITY
_VALIDATED1
SECOND_HIGH
EST_PRIORITY
_VALIDATED0
7
6
5
4
3
2
1
0
-
-
-
-
T0_INPUT_SEL3
T0_INPUT_SEL2
T0_INPUT_SEL1
T0_INPUT_SEL0
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