參數(shù)資料
型號: IDT82V3280PF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 通信及網絡
英文描述: WAN PLL
中文描述: SPECIALTY TELECOM CIRCUIT, PQFP100
封裝: TQFP-100
文件頁數(shù): 119/167頁
文件大?。?/td> 1039K
代理商: IDT82V3280PF
IDT82V3280
WAN PLL
Programming Information
119
June 19, 2006
T4_INPUT_SEL_CNFG - T4 Selected Input Clock Configuration
Address: 51H
Type: Read / Write
Default Value: X0000000
Bit
Name
Description
7
-
Reserved.
This bit determines whether the T4 DPLL locks to a T0 DPLL output or locks independently from the T0 DPLL.
0: Independently from the T0 path. (default)
1: Locks to a 77.76 MHz or 8 kHz signal from the T0 DPLL 77.76 MHz path.
This bit is valid only when the T4_LOCK_T0 bit (b6, 51H) is ‘1’. It determines whether a 77.76 MHz or 8 kHz signal from the
T0 DPLL 77.76 MHz path is selected by the T4 DPLL.
0: 77.76 MHz. (default)
1: 8 kHz.
This bit determines whether T4 selected input clock is compared with the feedback signal of the T4 DPLL for T4 DPLL locking
or is compared with the T0 selected input clock to get the phase difference between T0 and T4 selected input clocks.
0: The T4 DPLL output. (default)
1: The T0 selected input clock.
These bits are valid only when the T4_LOCK_T0 bit (b6, 51H) is ‘0’. They determines the T4 DPLL input clock selection.
0000: Automatic selection. (default)
0001: Forced selection - IN1 is selected.
0010: Forced selection - IN2 is selected.
......
1101: Forced selection - IN13 is selected.
1110: Forced selection - IN14 is selected.
1111: Reserved.
6
T4_LOCK_T0
5
T0_FOR_T4
4
T4_TEST_T0_PH
3 - 0
T4_INPUT_SEL[3:0]
7
6
5
4
3
2
1
0
-
T4_LOCK_T0
T0_FOR_T4
T4_TEST_T0_PH
T4_INPUT_SEL3
T4_INPUT_SEL2
T4_INPUT_SEL1
T4_INPUT_SEL0
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