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參數(shù)資料
| 型號： | IDT82V3280PF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | WAN PLL |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 8/167頁 |
| 文件大?。?/td> | 1039K |
| 代理商： | IDT82V3280PF |
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List of Figures
8
June 19, 2006
Figure 1. Functional Block Diagram ............................................................................................................................................................................ 11
Figure 2. Pin Assignment (Top View) .......................................................................................................................................................................... 12
Figure 3. Pre-Divider for An Input Clock ..................................................................................................................................................................... 21
Figure 4. Input Clock Activity Monitoring ..................................................................................................................................................................... 23
Figure 5. External Fast Selection ................................................................................................................................................................................ 25
Figure 6. Qualified Input Clocks for Automatic Selection ............................................................................................................................................ 26
Figure 7. T0 Selected Input Clock vs. DPLL Automatic Operating Mode ................................................................................................................... 32
Figure 8. T4 Selected Input Clock vs. DPLL Automatic Operating Mode ................................................................................................................... 33
Figure 9. On Target Frame Sync Input Signal Timing ................................................................................................................................................. 42
Figure 10. 0.5 UI Early Frame Sync Input Signal Timing ............................................................................................................................................. 42
Figure 11. 0.5 UI Late Frame Sync Input Signal Timing .............................................................................................................................................. 43
Figure 12. 1 UI Late Frame Sync Input Signal Timing ................................................................................................................................................. 43
Figure 13. Physical Connection Between Two Devices .............................................................................................................................................. 44
Figure 14. IDT82V3280 Power Decoupling Scheme ................................................................................................................................................... 46
Figure 15. Typical Application ...................................................................................................................................................................................... 47
Figure 16. EPROM Access Timing Diagram ............................................................................................................................................................... 49
Figure 17. Multiplexed Read Timing Diagram ............................................................................................................................................................. 50
Figure 18. Multiplexed Write Timing Diagram .............................................................................................................................................................. 51
Figure 19. Intel Read Timing Diagram ......................................................................................................................................................................... 52
Figure 20. Intel Write Timing Diagram ......................................................................................................................................................................... 53
Figure 21. Motorola Read Timing Diagram .................................................................................................................................................................. 54
Figure 22. Motorola Write Timing Diagram .................................................................................................................................................................. 55
Figure 23. Serial Read Timing Diagram (CLKE Asserted Low) ................................................................................................................................... 56
Figure 24. Serial Read Timing Diagram (CLKE Asserted High) .................................................................................................................................. 56
Figure 25. Serial Write Timing Diagram ....................................................................................................................................................................... 57
Figure 26. JTAG Interface Timing Diagram ................................................................................................................................................................. 58
Figure 27. 64 kHz + 8 kHz Signal Structure .............................................................................................................................................................. 151
Figure 28. 64 kHz + 8 kHz + 0.4 kHz Signal Structure .............................................................................................................................................. 151
Figure 29. 64 kHz + 8 kHz / 64 kHz + 8 kHz + 0.4 kHz Signal Input Level ................................................................................................................ 151
Figure 30. 64 kHz + 8 kHz / 64 kHz + 8 kHz + 0.4 kHz Signal Output Level ............................................................................................................. 151
Figure 31. AMI Input / Output Port Line Termination (Recommended) ..................................................................................................................... 152
Figure 32. Recommended PECL Input Port Line Termination .................................................................................................................................. 154
Figure 33. Recommended PECL Output Port Line Termination ................................................................................................................................ 154
Figure 34. Recommended LVDS Input Port Line Termination .................................................................................................................................. 156
Figure 35. Recommended LVDS Output Port Line Termination ................................................................................................................................ 156
Figure 36. Output Wander Generation ...................................................................................................................................................................... 160
Figure 37. Input / Output Clock Timing ...................................................................................................................................................................... 161
List of Figures
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT82V3280PFG | WAN PLL |
| IDT82V3288 | WAN PLL |
| IDT82V3288BC | WAN PLL |
| IDT82V3288BCG | WAN PLL |
| IDT85304-01 | LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT82V3280PFBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3280PFG | 功能描述:IC PLL WAN SE STRATUM 2 100-TQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| IDT82V3280PFG8 | 功能描述:IC PLL WAN SE STRATUM 2 100-TQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| IDT82V3280PFGBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3285 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL |
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