參數(shù)資料
型號： IDT82V3280PF
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 通信及網(wǎng)絡(luò)
英文描述： WAN PLL
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP100
封裝： TQFP-100
文件頁數(shù)： 4/167頁
文件大?。?/td> 1039K
代理商： IDT82V3280PF
Table of Contents
4
June 19, 2006
IDT82V3280
WAN PLL
3.10.1.3.1 Temp-Holdover Mode .................................................................................................................................... 34
3.10.1.4 Lost-Phase Mode ............................................................................................................................................................. 34
3.10.1.5 Holdover Mode ................................................................................................................................................................. 34
3.10.1.5.1 Automatic Instantaneous ............................................................................................................................... 35
3.10.1.5.2 Automatic Slow Averaged ............................................................................................................................. 35
3.10.1.5.3 Automatic Fast Averaged .............................................................................................................................. 35
3.10.1.5.4 Manual ........................................................................................................................................................... 35
3.10.1.5.5 Holdover Frequency Offset Read .................................................................................................................. 35
3.10.1.6 Pre-Locked2 Mode ........................................................................................................................................................... 35
3.10.2 T4 DPLL Operating Mode .............................................................................................................................................................. 35
3.10.2.1 Free-Run Mode ................................................................................................................................................................ 35
3.10.2.2 Locked Mode .................................................................................................................................................................... 35
3.10.2.3 Holdover Mode ................................................................................................................................................................. 35
3.11 T0 / T4 DPLL OUTPUT .................................................................................................................................................................................37
3.11.1 PFD Output Limit ............................................................................................................................................................................ 37
3.11.2 Frequency Offset Limit .................................................................................................................................................................. 37
3.11.3 PBO (T0 only) ................................................................................................................................................................................. 37
3.11.4 Phase Offset Selection (T0 only) .................................................................................................................................................. 37
3.11.5 Four Paths of T0 / T4 DPLL Outputs ............................................................................................................................................. 37
3.11.5.1 T0 Path ............................................................................................................................................................................. 37
3.11.5.2 T4 Path ............................................................................................................................................................................. 38
3.12 T0 / T4 APLL .................................................................................................................................................................................................39
3.13 OUTPUT CLOCKS & FRAME SYNC SIGNALS ...........................................................................................................................................39
3.13.1 Output Clocks ................................................................................................................................................................................. 39
3.13.2 Frame SYNC Output Signals ......................................................................................................................................................... 42
3.14 MASTER / SLAVE CONFIGURATION .........................................................................................................................................................44
3.15 INTERRUPT SUMMARY ...............................................................................................................................................................................45
3.16 T0 AND T4 SUMMARY .................................................................................................................................................................................45
3.17 POWER SUPPLY FILTERING TECHNIQUES .............................................................................................................................................46
4 TYPICAL APPLICATION .................................................................................................................................................47
4.1
MASTER / SLAVE APPLICATION ...............................................................................................................................................................47
5 MICROPROCESSOR INTERFACE ..................................................................................................................................48
5.1
EPROM MODE ..............................................................................................................................................................................................49
5.2
MULTIPLEXED MODE ..................................................................................................................................................................................50
5.3
INTEL MODE .................................................................................................................................................................................................52
5.4
MOTOROLA MODE ......................................................................................................................................................................................54
5.5
SERIAL MODE ..............................................................................................................................................................................................56
6 JTAG ................................................................................................................................................................................58
7 PROGRAMMING INFORMATION ....................................................................................................................................59
7.1
REGISTER MAP ............................................................................................................................................................................................59
7.2
REGISTER DESCRIPTION ...........................................................................................................................................................................65
7.2.1
Global Control Registers ............................................................................................................................................................... 65
7.2.2
Interrupt Registers ......................................................................................................................................................................... 74
7.2.3
Input Clock Frequency & Priority Configuration Registers ....................................................................................................... 79
7.2.4
Input Clock Quality Monitoring Configuration & Status Registers ......................................................................................... 102
7.2.5
T0 / T4 DPLL Input Clock Selection Registers ........................................................................................................................... 116
7.2.6
T0 / T4 DPLL State Machine Control Registers ......................................................................................................................... 120
7.2.7
T0 / T4 DPLL & APLL Configuration Registers .......................................................................................................................... 122
7.2.8
Output Configuration Registers .................................................................................................................................................. 136
7.2.9
PBO & Phase Offset Control Registers ...................................................................................................................................... 146
7.2.10 Synchronization Configuration Registers ................................................................................................................................. 148
8 THERMAL MANAGEMENT ...........................................................................................................................................149
8.1
JUNCTION TEMPERATURE ......................................................................................................................................................................149
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IDT82V3280PFBLANK 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL
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IDT82V3280PFG8 功能描述:IC PLL WAN SE STRATUM 2 100-TQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT
IDT82V3280PFGBLANK 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL
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