參數(shù)資料
型號(hào)： IDT8737-11PGG8
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi)： 時(shí)鐘及定時(shí)
英文描述： 8737 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
封裝： GREEN, TSSOP-20
文件頁(yè)數(shù)： 12/12頁(yè)
文件大小： 98K
代理商： IDT8737-11PGG8
9
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
IDT8737-11
LOW SKEW,
÷÷÷÷÷1/÷÷÷÷÷2 DIFFERENTIAL-TO-3.3V LVPECL
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE-ENDED LEVELS
The diagram below shows how the differential input can be wired to accept single-ended levels. The reference voltage VREF
VDD/2isgeneratedbythe
bias resistors R1, R2, and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to
position the VREF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, VREF should be 1.25V and R2/
R1 = 0.609.
Single-Ended Signal Driving Differential Input
VDD
VREF
+
-
C1
0.1uF
CLK_IN
R1
1K
R2
1K
TERMINATION FOR LVPECL OUTPUTS
TheclocklayouttopologyshownbelowisatypicalterminationforLVPECLoutputs. Thetwodifferentlayoutsmentionedarerecommendedonlyasguidelines.
FOUT and xFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to
ground) or current sources must be used for functionality. These outputs are designed to drive 50
Ωtransmissionlines. Matchedimpedancetechniquesshould
be used to maximize operating frequency and minimize signal distortion. The diagrams below show two different layouts which are recommended only as
guidelines. Other suitable clock layouts may exist. It is recommended that the board designers simulate to guarantee compatibility across all printed circuit and
clock component process variations.
LVPECL Output Termination, layout A
LVPECL Output Termination, layout B
FOUT
50
Ω
50
Ω
Zo = 50
Ω
VDD - 2V
Zo = 50
Ω
RTT
FIN
RTT =
(VOH + VOL / VDD - 2) - 2
1
Zo
FOUT
Zo = 50
Ω
Zo = 50
Ω
FIN
Zo
3
2
Zo
3
2
Zo
5
2
Zo
5
2
3.3V
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