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參數資料
| 型號： | IDTCSPT857PA8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | CSPT857 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封裝： | TSSOP-48 |
| 文件頁數： | 1/12頁 |
| 文件大?。?/td> | 128K |
| 代理商： | IDTCSPT857PA8 |
1
IDTCSPT857/A
2.5V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
2002
Integrated Device Technology, Inc.
DSC-5172/9
c
IDTCSPT857/A
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
2.5V PHASE LOCKED LOOP
DIFFERENTIAL 1:10 SDRAM
CLOCK DRIVER
Y0
FBOUT
Y1
Y5
Y4
Y3
Y2
Y8
Y6
Y7
Y9
FBOUT
3/A1
2/A2
5/B2
6/B1
10/D1
9/D2
20/J2
19/J1
22/K1
23/K2
46/A6
47/A5
44/B5
43/B6
39/D6
40/D5
29/J5
30/J6
27/K6
26/K5
32/H6
33/H5
PLL
CLK
PWRDWN
37/E6
CLK
13/F1
14/F2
36/F6
35/F5
16/G2
FBIN
TEST
MODE
LOGIC
AVDD
OCTOBER 2002
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
Optimized for clock distribution in DDR (Double Data Rate)
SDRAM applications
Operating frequency: 60MHz to 200MHz
Standard speed: PC1600 (DDR200), PC2100 (DDR266)
A speed: PC1600 (DDR200), PC2100 (DDR266), PC2700 (DDR333)
1 to 10 differential clock distribution
Very low skew (<100ps)
Very low jitter (<75ps)
2.5V AVDD and 2.5V VDDQ
CMOS control signal input
Test mode enables buffers while disabling PLL
Low current power-down mode
Tolerant of Spread Spectrum input clock
Available in 48-pin TSSOP and 56-pin VFBGA packages
DESCRIPTION:
The CSPT857 is a PLL based clock driver that acts as a zero delay buffer
to distribute one differential clock input pair(CLK,
CLK)to10differentialoutput
pairs (Y[0:9], Y[0:9]) and one differential pair of feedback clock output (FBOUT,
FBOUT). External feedback pins (FBIN, FBIN) for synchronization of the
outputs to the input reference is provided. A CMOS Enable/Disable pin is
available for low power disable. When the output frequency falls below
approximately 20MHz, the device will enter power down mode. In this mode,
the receivers are disabled, the PLL is turned off, and the output clock drivers
are tristated, resulting in a current consumption device of less than 200
μA.
The CSPT857 requires no external components and has been optimised
for very low I/O phase error, skew, and jitter, while maintaining frequency and
duty cycle over the operating voltage and temperature range. The CSPT857,
designed for use in both module assemblies and system motherboard based
solutions, provides an optimum high-performance clock source.
The CSPT857 is only available in Industrial Temperature Range (-40°C to
+85°C), and CSPT857A is only available in Commercial Temperature Range
(0°C to +70°C). See Ordering Information for details.
FUNCTIONAL BLOCK DIAGRAM
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| IDTCSPT857CPAI8 | 857 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| IDTCSPT857PAI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:2.5V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| IDTCSPU877A | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| IDTCSPU877ABV | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| IDTCSPU877ABVG | 功能描述:IC SDRAM CLK DVR 1:10 52-VFBGA RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1 系列:- 類型:時鐘/頻率發(fā)生器，多路復用器 PLL:是 主要目的:存儲器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數:1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6 |
| IDTCSPU877ABVG8 | 功能描述:IC PLL CLK DVR SDRAM 56-CABGA RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務器 輸入:時鐘 輸出:LVCMOS 電路數:1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應商設備封裝:64-TSSOP 包裝:管件 |
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