參數(shù)資料
型號: IDT89HPES24NT3ZBBXG8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 30/31頁
文件大?。?/td> 0K
描述: IC PCI SW 24LANE 3PORT 420-SBGA
標(biāo)準(zhǔn)包裝: 250
系列: PRECISE™
類型: PCI Express 開關(guān) - Gen1
應(yīng)用: 服務(wù)器,儲存,通信,嵌入式,消費品
安裝類型: 表面貼裝
封裝/外殼: 420-LBGA
供應(yīng)商設(shè)備封裝: 420-SBGA(27x27)
包裝: 帶卷 (TR)
其它名稱: 89HPES24NT3ZBBXG8
8 of 31
January 5, 2009
IDT 89HPES24NT3 Data Sheet
Pin Characteristics
Note: Some input pads of the PES24NT3 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate
levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left
floating can cause a slight increase in power consumption.
Function
Pin Name
Type
Buffer
I/O Type Internal
Resistor
Notes
PCI Express Inter-
face
PEALREV
I
LVTTL
Input
pull-down
PEARN[7:0]
I
CML
Serial link
PEARP[7:0]
I
PEATN[7:0]
O
PEATP[7:0]
O
PEBLREV
I
LVTTL
Input
pull-down
PEBRN[7:0]
I
CML
Serial link
PEBRP[7:0]
I
PEBTN[7:0]
O
PEBTP[7:0]
O
PECLREV
I
LVTTL
Input
pull-down
PECRN[7:0]
I
CML
Serial link
PECRP[7:0]
I
PECTN[7:0]
O
PECTP[7:0]
O
PEREFCLKN[1:0]
I
LVPECL/
CML
Diff. Clock
Input
Refer to
PEREFCLKP[1:0]
I
REFCLKM
I
LVTTL
Input
pull-down
SMBus
MSMBADDR[4:1]
I
LVTTL
Input
pull-up
MSMBCLK
I/O
STI
MSMBDAT
I/O
SSMBADDR[5,3:1]
I
Input
pull-up
SSMBCLK
I/O
STI
SSMBDAT
I/O
General Purpose I/O
GPIO[7:0]
I/O
LVTTL
Input,
High Drive
pull-up
System Pins
CCLKDS
I
LVTTL
Input
pull-up
CCLKUS
I
pull-up
MSMBSMODE
I
pull-down
PENTBRSTN
I
PERSTN
I
RSTHALT
I
pull-down
SWMODE[3:0]
I
pull-up
Table 7 Pin Characteristics (Part 1 of 2)
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