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參數資料
| 型號： | IDTCSP2510DPGI8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數： | 3/9頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK DVR PLL ZDB 1:10 24TSSOP |
| 標準包裝： | 3,000 |
| 類型： | 驅動器，PLL，零延遲緩沖器 |
| PLL： | 帶旁路 |
| 輸入： | 時鐘 |
| 輸出： | 時鐘 |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 1:10 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 175MHz |
| 除法器/乘法器： | 無/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 24-TSSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | CSP2510DPGI8 |
3
0
°CTO85°CTEMPERATURERANGE
IDTCSP2510D
3.3V PHASE-LOCK LOOP CLOCK DRIVER
STATIC FUNCTION TABLE (AVDD=0V)
DYNAMIC FUNCTION TABLE (AVDD=3.3V)
PIN DESCRIPTION
Terminal
Name
No.
Type
Description
CLK
24
I
Clock input. CLK provides the clock signal to be distributed by the CSP2510D clock driver. CLK is used to provide the reference signal
totheintegratedPLLthatgeneratestheclockoutputsignals.CLKmusthaveafixedfrequencyandfixedphaseforthePLLtoobtainphase
lock. OncethecircuitispoweredupandavalidCLKsignalisapplied,astabilizationtimeisrequiredforthePLLtophaselockthefeedback
signal to its reference signal.
FBIN
13
I
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to FBOUT to complete the PLL. The
integrated PLL synchronizes CLK and FBIN so that there is nominally zero phase error between CLK and FBIN.
G
11
I
Output bank enable. G is the output enable for outputs Y(0:9). When G is low, outputs Y(0:9) are disabled to a logic-low state. When
G is high, all outputs Y(0:9) are enabled and switch at the same frequency as CLK.
FBOUT
12
O
Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK. When externally wired to
FBIN, FBOUT completes the feedback loop of the PLL.
Y (0:9)
3, 4, 5, 8, 9,
O
Clock outputs. These outputs provide low-skew copies of CLK. Output bank Y(0:9) is enabled via the G input. These outputs can be
15, 16, 17,
disabled to a logic-low state by de-asserting the G control input.
20, 21
AVDD
23
Power
Analog power supply. AVDD provides the power reference for the analog circuitry. In addition, AVDD can be used to bypass the PLL
for test purposes. When AVDD is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs.
AGND
1
Ground
Analog ground. AGND provides the ground reference for the analog circuitry.
VDD
2, 10, 14, 22 Power
Power supply
GND
6, 7, 18, 19
Ground
Inputs
Outputs
G
CLK
Y (0:9)
FBOUT
LL
L
LH
L
H
HH
H
HL
L
H
running
Inputs
Outputs
G
CLK
Y (0:9)
FBOUT
XL
L
running
L
runningin
phase with CLK
LH
L
H
running
runningin
phase with CLK
HH
H
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