- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9026 > IDTCSP2510DPGI8 (IDT, Integrated Device Technology Inc)IC CLK DVR PLL ZDB 1:10 24TSSOP PDF資料下載
參數(shù)資料
| 型號： | IDTCSP2510DPGI8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 4/9頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK DVR PLL ZDB 1:10 24TSSOP |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 類型： | 驅(qū)動器，PLL，零延遲緩沖器 |
| PLL： | 帶旁路 |
| 輸入： | 時鐘 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:10 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 175MHz |
| 除法器/乘法器： | 無/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | CSP2510DPGI8 |
4
0
°CTO85°CTEMPERATURERANGE
IDTCSP2510D
3.3V PHASE-LOCK LOOP CLOCK DRIVER
DC ELECTRICAL CHARACTERISTICS OVER OPERATING FREE-AIR TEMPERA-
TURE RANGE(1)
Symbol
Description
Test Conditions
VDD
Min.
Typ.
(2)
Max.
Unit
VIK
Input Clamp Voltage
II = -18mA
3V
– 1.2
V
VIH
Input HIGH Level
2
V
VIL
Input LOW Level
0.8
V
IOH = -100
μA
Min. to Max.
VDD – 0.2
VOH
HIGH Level Output Voltage
IOH = -12mA
3V
2.1
V
IOH = -6mA
3V
2.4
IOL = 100
μA
Min. to Max.
0.2
VOL
LOW Level Output Voltage
IOL = 12mA
3V
0.8
V
IOL = 6mA
3V
0.55
II
InputCurrent
VI = VDD or GND
3.6V
±5
μA
IDD
Supply Current
VI = VDD or GND, AVDD = GND,
3.6V
10
μA
IO = 0, Outputs: LOW or HIGH
ΔIDD
Change in Supply Current
One input at VDD - 0.6V, other inputs at VDD or GND
3.3V to 3.6V
500
μA
CPD
Power Dissipation Capacitance
3.6V
10
14
pF
IDDA
(3)
AVDD Power Supply Current
AVDD = 3.3V
10
mA
NOTES:
1. For Industrial devices, operating free-air temperature = -40°C to +85°C.
2. For conditions shown as Min. or Max., use the appropriate value specified under recommended operating conditions.
3. For IDD of AVDD, see TYPICAL CHARACTERISTICS.
Min.
Max.
Unit
Clock frequency
50
175
MHz
fCLOCK
Input clock duty cycle
40%
60%
Stabilizationtime(2)
1ms
TIMING REQUIREMENTS OVER OPERATING RANGE OF SUPPLY VOLTAGE AND
OPERATING FREE-AIR TEMPERATURE(1)
NOTES:
1. For Industrial devices, operating free-air temperature = -40°C to +85°C.
2. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase
reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics
table are not applicable.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VE-B31-MV-F3 | CONVERTER MOD DC/DC 12V 150W |
| VE-B31-MV-F2 | CONVERTER MOD DC/DC 12V 150W |
| W134MHT | IC CLK DIFF DIRECT RAMBUS 24QSOP |
| VE-2NY-MU-F4 | CONVERTER MOD DC/DC 3.3V 132W |
| VE-23P-MW-F4 | CONVERTER MOD DC/DC 13.8V 100W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDTCSP5940Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Ten Distributed-Output Clock Driver |
| IDTCSPF2510C | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V PHASE-LOCK LOOP CLOCK DRIVER |
| IDTCSPF2510CPG | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V PHASE-LOCK LOOP CLOCK DRIVER |
| IDTCSPF2510CPGG | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V PHASE-LOCK LOOP CLOCK DRIVER |
| IDTCSPF2510CPGGI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V PHASE-LOCK LOOP CLOCK DRIVER |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。