°CTO85°CTEMPERATURERANGE IDTCSP2510D 3.3V PHASE-LOCK " />
參數(shù)資料
型號(hào): IDTCSP2510DPGI8
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 6/9頁(yè)
文件大?。?/td> 0K
描述: IC CLK DVR PLL ZDB 1:10 24TSSOP
標(biāo)準(zhǔn)包裝: 3,000
類型: 驅(qū)動(dòng)器,PLL,零延遲緩沖器
PLL: 帶旁路
輸入: 時(shí)鐘
輸出: 時(shí)鐘
電路數(shù): 1
比率 - 輸入:輸出: 1:10
差分 - 輸入:輸出: 無/無
頻率 - 最大: 175MHz
除法器/乘法器: 無/無
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 帶卷 (TR)
其它名稱: CSP2510DPGI8
6
0
°CTO85°CTEMPERATURERANGE
IDTCSP2510D
3.3V PHASE-LOCK LOOP CLOCK DRIVER
From Output
Under Test
500
Ω
Y
CF
FBIN
CLK
CSP2510D
FBOUT
PCBTRACE
CL = 30pF(2)
500
Ω
on each
Y output
CLK
tPHASE ERROR
FBIN
FBOUT
tSK(o)
Any Y
tSK(o)
Any Y
Input
Output
or
FBIN
50% VDD
tR
tF
2V
0.4V
3V
0V
2V
0.4V
tPHASE ER ROR
VOL
VOH
CL = 30pF(2)
PARAMETER MEASUREMENT INFORMATION(1)
NOTES:
1. All inputs pulses are supplied by generators having the following characteristics: PRR
≤ 100MHz ZO = 50Ω, tR ≤ 1.2 ns, tF≤ 1.2 ns.
2. CL includes probe and jig capacitance.
3. The outputs are measured one at a time with one transition per measurement.
4. Phase error measurements require equal loading at outputs Y and FBOUT. CF = CL – CFBIN – CPCBTRACE; CFBIN
6pF.
Load Circuit and Voltage Waveforms
Phase ERROR and Skew Calculations (3,4)
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