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參數(shù)資料
| 型號： | IDTCSPT857PA8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | CSPT857 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封裝： | TSSOP-48 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 128K |
| 代理商： | IDTCSPT857PA8 |
6
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
IDTCSPT857/A
2.5V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
TIMING REQUIREMENTS
Symbol
Parameter
Min.
Max.
Unit
fCLK
Operating Clock Frequency(1,2)
60
200
MHz
Application Clock Frequency(1,3)
60
200
MHz
tDC
Input Clock Duty Cycle
40
60
%
tL
StabilizationTime(4)
100
μs
NOTES:
1.
The PLL will track a spread spectrum clock input.
2.
Operating clock frequency is the range over which the PLL will lock, but may not meet all timing specifications.
3.
Application clock frequency is the range over which timing specifications apply.
4.
Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up.
SWITCHINGCHARACTERISTICS
CSPT857
CSPT857A
Symbol
Description
Test Conditions
Min.
Typ.(1) Max.
Min.
Typ.(1)
Max.
Unit
tPLH(1)
LOW to HIGH Level Propagation Delay Time
Test mode, CLK to any output
4.5
ns
tPHL(1)
HIGH to LOW Level Propagation Delay Time
Test mode, CLK to any output
4.5
ns
tJIT(PER)
Jitter (period), see figure 6
66MHz
– 90
90
– 90
90
ps
100/ 133/ 167/ 200 MHz
– 75
75
– 75
75
tJIT(CC)
Jitter (cycle-to-cycle), see figure 3
66MHz
– 180
180
– 180
180
ps
100/ 133/ 167/ 200 MHz
– 75
75
– 75
75
tJIT(HPER)
Half-Period Jitter, see figure 7
66MHz
– 160
160
– 160
160
ps
100/ 133/ 167/ 200 MHz
– 100
100
– 100
100
tSLR(O)
Output Clock Slew Rate (Single-Ended)
100/ 133/ 167/ 200 MHz (20% to 80%)
1
2
1
2
V/ns
tSLR(I)
Input Clock Slew Rate
1
4
1
4
V/ns
t(
)
Static Phase Offset, see figure 4(2,3)
66/ 100/ 133/ 167/ 200 MHz
– 100
100
– 50
50
ps
tSK(O)
Output Skew, see figure 5
75
ps
tR,tF
Output Rise and Fall Times (20% to 80%)
Load: 120
Ω / 14pF
650
900
650
900
ps
VOX(5)
OutputDifferentialVoltage
Differentialoutputsareterminated
VDDQ/2
VDDQ/2 VDDQ/2
VDDQ/2
V
with 120
Ω
– 0.2
+ 0.2
– 0.15
+ 0.15
The PLL on the CSPT857 will meet all the above test parameters while supporting SSC synthesizers(4) with the following parameters:
SSC
ModulationFrequency
30
50
30
50
KHz
SSC
Clock Input Frequency Deviation
0
-0.5
0
-0.5
%
f3dB
PLL Loop Bandwidth
5
5
MHz
NOTES:
1.
Refers to transition of non-inverting output.
2.
Static phase offset does not include jitter.
3.
t(
φ) is measured with input clock slew rate tSLR(I) = 2V/ns and an input differential voltage VID of 1.75V.
4.
The SSC requirements meet the Intel PC100 SDRAM Registered DIMM specification.
5.
VOX is specified at the SDRAM clock input or test load.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDTCSPT857PAI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:2.5V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| IDTCSPU877A | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| IDTCSPU877ABV | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
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| IDTCSPU877ABVG8 | 功能描述:IC PLL CLK DVR SDRAM 56-CABGA RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應商設備封裝:64-TSSOP 包裝:管件 |
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