參數(shù)資料
型號： IDTCSPT857PA8
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： CSPT857 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
封裝： TSSOP-48
文件頁數(shù)： 7/12頁
文件大?。?/td> 128K
代理商： IDTCSPT857PA8
4
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
IDTCSPT857/A
2.5V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
Z = High-Impedance OFF-State
X = Don't Care
2. Additional feature that senses when the clock input is less than approximately 20MHz and places the part in sleep mode. Reciever inputs and PLL are turned off and outputs
= tristate.
FUNCTION TABLE(1)
INPUTS
OUTPUTS
AVDD
PWRDWN
CLK
Y
FBOUT
PLL
GND
H
L
H
L
H
L
H
Bypassed/OFF
GND
H
L
H
L
H
L
Bypassed/OFF
X
L
H
Z
OFF
X
L
H
L
Z
OFF
2.5V (nom)
H
L
H
L
H
L
H
O N
2.5V (nom)
H
L
H
L
H
L
O N
2.5V (nom)(2)
X
<20MHz
Z
OFF
PIN DESCRIPTION (TSSOP)
Pin Name
Pin Number
Description
AGND
17
Ground for 2.5V analog supply
AVDD
16
2.5V analog supply
CLK,
CLK
13, 14
Differentialclockinput
FBIN, FBIN
35, 36
Feedbackdifferentialclockinput
FBOUT,
FBOUT
32, 33
Feedbackdifferentialclockoutput
GND
1, 7, 8, 18, 24, 25, 31, 41, 42, 48
Ground
PWRDWN
37
Output enable for Y and
Y
VDDQ
4, 11, 12, 15, 21, 28, 34, 38, 45
2.5V supply
Y[0:9]
3, 5, 10, 20, 22, 27, 29, 39, 44, 46
Buffered output of input clock, CLK
Y[0:9]
2, 6, 9, 19, 23, 26, 30, 40, 43, 47
Buffered output of input clock,
CLK
PIN DESCRIPTION (VFBGA)
Pin Name
Pin Number
Description
AGND
H1
Ground for 2.5V analog supply
AVDD
G2
2.5V analog supply
CLK,
CLK
F1, F2
Differentialclockinput
FBIN, FBIN
F5, F6
Feedbackdifferentialclockinput
FBOUT,
FBOUT
H6, G5
Feedbackdifferentialclockoutput
GND
A3, A4, C1, C2, C5, C6, H2, H5, K3, K4
Ground
PWRDWN
E6
Output enable for Y and
Y
VDDQ
B3, B4, E1, E2, E5, G1, G6, J3, J4
2.5V supply
Y[0:9]
A1, A6, B2, B5, D1, D6, J2, J5, K1, K6
Buffered output of input clock, CLK
Y[0:9]
A2, A5, B1, B6, D2, D5, J1, J6, K2, K5
Buffered output of input clock,
CLK
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