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參數(shù)資料
| 型號(hào)： | IDTCSPU877ANLG8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 877 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC40 |
| 封裝： | GREEN, PLASTIC, MLF-40 |
| 文件頁數(shù)： | 7/13頁 |
| 文件大小： | 115K |
| 代理商： | IDTCSPU877ANLG8 |
3
IDTCSPU877A
1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIALTEMPERATURERANGE
ABSOLUTE MAXIMUM RATINGS(1,2)
Symbol
Rating
Max
Unit
VDDQ, AVDD
SupplyVoltageRange
–0.5 to +2.5
V
VI(3)
InputVoltageRange
–0.5 to VDDQ + 0.5
V
VO(3)
Voltagerangeappliedtoany
–0.5 to VDDQ + 0.5
V
output in the high or low state
IIK
Input clamp current
±50
mA
(VI <0)
IOK
Output Clamp Current
±50
mA
(VO <0 or
VO > VDDQ)
IO
Continuous Output Current
±50
mA
(VO =0 to VDDQ)
VDDQ or GND
Continuous Current
±100
mA
TSTG
Storage Temperature Range
– 65 to +150
°C
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. The maximum package power dissipation is calculated using a junction temperature
of 150
°C and a board trace length of 750 mils.
3. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed. This value is limited to 2.5V max.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min.
Typ.
Max.
Unit
AVDD(1)
SupplyVoltage
VDDQ
V
VDDQ
I/O Supply Voltage
1.7
1.8
1.9
V
TA
OperatingFree-AirTemperature
0
+70
°C
CAPACITANCE(1)
Parameter
Description
Min.
Typ.
Max.
Unit
CIN
Input Capacitance
2
—
3
pF
VI = VDDQ or GND
CI
Δ
DeltaInputCapacitance
0.25
pF
CLK, CLK, FBIN, FBIN
CL
LoadCapacitance
—
10
—
pF
NOTE:
1. Unused inputs must be held high or low to prevent them from floating.
VFQFPN
TOP VIEW
NOTE:
1. The PLL is turned off and bypassed for test purposes when AVDD is grounded. During this test mode, VDDQ remains within the recommended operating conditions and no timing
parameters are guaranteed.
PIN CONFIGURATION, CONT.
V
D
Q
Y
5
Y
6
Y
6
Y
0
Y
5
Y
0
Y
1
Y
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
2
3
1
V
D
Q
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
Y
3
Y
3
V
D
Q
Y
4
Y
4
Y
8
Y
8
Y
9
Y
9
V
D
Q
VDDQ
Y7
FBIN
FBOUT
30
29
28
27
26
25
24
23
22
21
FBOUT
OE
OS
Y7
VDDQ
GND
VDDQ
Y2
AGND
AVDD
CLK
VDDQ
2
3
4
5
6
7
8
1
9
10
VDDQ
GND
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