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參數(shù)資料
| 型號(hào)： | IDTCSPUA877BVG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 時(shí)鐘及定時(shí) |
| 英文描述： | CSPUA877 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), BGA52 |
| 封裝： | GREEN, VFBGA-52 |
| 文件頁(yè)數(shù)： | 1/14頁(yè) |
| 文件大?。?/td> | 116K |
| 代理商： | IDTCSPUA877BVG |
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IDTCSPUA877A
1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIALTEMPERATURERANGE
2006 Integrated Device Technology, Inc.
DSC 6872/3
c
IDTCSPUA877A
COMMERCIAL TEMPERATURE RANGE
1.8V PHASE LOCKED LOOP
DIFFERENTIAL 1:10 SDRAM
CLOCK DRIVER
OCTOBER 2006
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
1 to 10 differential clock distribution
Optimized for clock distribution in DDR2 (Double Data Rate)
SDRAM applications
Operating frequency: 125MHz to 410MHz
Stabilization time: <6us
Very low skew:
≤≤≤≤≤40ps
Very low jitter:
≤≤≤≤≤40ps
1.8V AVDD and 1.8V VDDQ
CMOS control signal input
Test mode enables buffers while disabling PLL
Low current power-down mode
Tolerant of Spread Spectrum input clock
Available in 52-Ball VFBGA and 40-pin VFQFPN packages
FUNCTIONAL BLOCK DIAGRAM
NOTE:
The Logic Detect (LD) powers down the device when a logic LOW is applied to both CLK and CLK.
DESCRIPTION:
TheCSPUA877AisaPLLbasedclockdriverthatactsasazerodelaybuffer
to distribute one differential clock input pair(CLK, CLK ) to 10 differential
output pairs (Y [0:9], Y [0:9]) and one differential pair of feedback clock output
(FBOUT,FBOUT). Externalfeedbackpins(FBIN, FBIN)forsynchronization
oftheoutputstotheinputreferenceisprovided.OE,OS,andAVDDcontrolthe
power-down and test mode logic. When AVDD is grounded, the PLL is turned
off and bypassed for test mode purposes. When the differential clock inputs
(CLK,CLK)arebothatlogiclow,thisdevicewillenteralowpower-downmode.
In this mode, the receivers are disabled, the PLL is turned off, and the output
clockdriversaredisabled,resultinginaclockdrivercurrentconsumptionofless
than500
μA.
TheCSPUA877Arequiresnoexternalcomponentsandhasbeenoptimised
forverylowphaseerror,skew,andjitter,whilemaintainingfrequencyandduty
cycle over the operating voltage and temperature range. The CSPUA877 ,
designedforuseinbothmoduleassembliesandsystemmotherboardbased
solutions,providesanoptimumhigh-performanceclocksource.
TheCSPUA877AisavailableinCommercialTemperatureRange(0°Cto
+70°C). See Ordering Information for details.
APPLICATIONS:
Meets or exceeds JEDEC standard CUA877 for registered DDR2
clock driver
Along with SSTUA32864/66, DDR2 register, provides complete
solution for DDR2 DIMMs
Y0
FBOUT
Y1
Y5
Y4
Y3
Y2
Y8
Y6
Y7
Y9
FBOUT
FBIN
PLL
CLK
POWER
DOWN
AND
TEST
MODE
LOGIC
LD
AVDD
OE
OS
LD or OE
LD, OS, or OE
PLL BYPASS
10K
Ω -100KΩ
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