參數(shù)資料
型號(hào)： IDTCV107EPVG8
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘產(chǎn)生/分配
英文描述： 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝： SSOP-48
文件頁(yè)數(shù)： 1/21頁(yè)
文件大?。?/td> 108K
代理商： IDTCV107EPVG8
COMMERCIALTEMPERATURERANGE
IDTCV107E
CLOCKGENERATORFORDESKTOPPCPLATFORMS
1
JANUARY 2004
COMMERCIAL TEMPERATURE RANGE
XTAL
Osc Amp
SM Bus
Controller
Watch Dog
Timer
Control
Logic
CPU CLK
Output Buffers
AGP/PCI
Output Buffers
SRC CLK
Output Buffer
48MHz
Output Buffer
X1
X2
SDATA
SCLK
VTT_PWRGD
FS[1:0]
SEL24_48#
IREF
CPU[1:0]
REF 2.1.0
PCI[5:0], PCIF[2:0]
3V66[3:0]
SRC
48MHz[1:0]
24 - 48MHz
PLL3
SSC
PLL4
PLL1
SSC
EasyN
Programming
PLL2
SSC
EasyN
Programming
RESET#
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2004 Integrated Device Technology, Inc.
DSC-6390/15
FUNCTIONAL BLOCK DIAGRAM
OUTPUTTABLE
CPU (Pair)
3V66
3V66/VCH
PCI
PCIF
REF
48MHz
24 - 48MHz
SRC (Pair)
Reset#
23
1
6
332
1
IDTCV107E
CLOCK GENERATOR FOR
DESKTOP PC PLATFORMS
FEATURES:
4 PLL architecture
Linear frequency programming
Independent frequency programming and SSC control
Band-gap circuit for differential output
High power-noise rejection ratio
66MHz to 533MHz CPU frequency
VCO frequency up to 1.1G
Support index block read/write, single cycle index block read
Programmable REF, 3V66, PCI, 48MHz I/O drive strength
Programmable 3V66 and PCI Skew
Available in SSOP package
DESCRIPTION:
IDTCV107E is a 48 pin clock generation device for desktop PC platforms.
ThischipincorporatesfourPLLstoallowindependentgenerationofCPU,AGP/
PCI, SRC, and 48MHz clocks. The dedicated PLL for Serial ATA clock
provides high accuracy frequency. This device also implements Band-gap
referenced IREF to reduce the impact of VDD variation on differential outputs,
which can provide more robust system performance.
Static PLL frequency divide error can be as low as 36 ppm, providing high
accuracy output clock. Each CPU, AGP/PCI, SRC clock has its own Spread
Spectrumselection.
KEY SPECIFICATION:
CPU/SRC CLK cycle to cycle jitter < 125ps
SATA CLK cycle to cycle jitter < 125ps
PCI CLK cycle to cycle jitter < 250ps
Static PLL frequency divide error as low as 36 ppm
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