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參數(shù)資料
| 型號： | IDTCSPUA877BVG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | CSPUA877 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), BGA52 |
| 封裝： | GREEN, VFBGA-52 |
| 文件頁數(shù)： | 11/14頁 |
| 文件大?。?/td> | 116K |
| 代理商： | IDTCSPUA877BVG |
6
COMMERCIALTEMPERATURERANGE
IDTCSPUA877A
1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to +70°C
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
VIK
InputClampVoltage(AllInputs)
VDDQ = 1.7V, II = -18mA
– 1.2
V
VIL(2)
Input LOW Voltage (OE, OS, CLK, CLK)
0.35VDDQ
V
VIH(2)
Input HIGH Voltage (OE, OS, CLK, CLK)
0.65VDDQ
VIN(1)
InputSignalVoltage
-0.3
VDDQ + 0.3
V
VID(DC)(2)
DCInputDifferentialVoltage
0.3
VDDQ + 0.4
V
VOD(3)
OutputDifferentialVoltage
AVDD/VDDQ = 1.7V
0.6
V
VOH
Output HIGH Voltage
IOH = -100
μA, VDDQ = 1.7V to 1.9V
VDDQ - 0.2
V
IOH = -9mA, VDDQ = 1.7V
1.1
VOL
OutputLOWVoltage
IOL = 100
μA, VDDQ = 1.7V to 1.9V
0.1
V
IOL = 9mA, VDDQ = 1.7V
0.6
IODL
OutputDisabledLOWCurrent
OE = L, VODL = 100mV, AVDD/VDDQ = 1.7V
100
μA
IIN
InputCurrent CLK, CLK
AVDD/VDDQ = Max., VI = 0V to VDDQ
±250
μA
OE, OS, FBIN, FBIN
±10
IDDLD
Static Supply Current (IDDQ and IADD)AVDD/VDDQ = Max., CLK and CLK = GND
500
μA
IDD
Dynamic Power Supply Current
AVDD/VDDQ = Max., CLK = 410MHz
300
mA
(IDDQ andIADD)(4,5)
NOTES:
1. VIN specifies the allowable DC excursion of each different output.
2. VID is the magnitude of the difference between the input level on CLK and the input level on CLK. The CLK and CLK VIH and VIL limits are used to define the DC LOW and HIGH
levels for the power down mode.
3. VOD is the magnitude of the difference between the true output level and the complementary level.
4. All Outputs are left open (unconnected to PCB).
5. Total IDD = IDDQ + IADD = FCK * CPD * VDDQ, for Cpd = (IDDQ + IADD) / (FCK * VDDQ) where FCK is the input frequency, VDDQ is the power supply, and CPD is the Power Dissipation Capacitance.
TIMING REQUIREMENTS
Symbol
Parameter
Min.
Max.
Unit
fCLK
OperatingClockFrequency(1,2,5)
125
410
MHz
ApplicationClockFrequency(1,3,5)
160
410
MHz
tDC
Input Clock Duty Cycle
40
60
%
tL
StabilizationTime(4)
6
μs
NOTES:
1. The PLL will track a spread spectrum clock input.
2. Operating clock frequency is the range over which the PLL will lock, but may not meet all timing specifications. To be used only for low speed system debug.
3. Application clock frequency is the range over which timing specifications apply.
4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up. During normal operation, the
stabilization time is also the time required for the PLL circuit to obtain phase lock of its feedback signal to its reference signal when CLK and CLK go to a logic LOW state, enters
the power-down mode, and later return to active operation. CLK and CLK may be left floating after they have been driven LOW for one complete clock cycle.
5. Will lock to input frequency as low as 30MHz at room temperature and nominal or higher supply voltage (1.8V - 1.9V).
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