參數(shù)資料
型號: IDTCV115FPVG8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 4/19頁
文件大?。?/td> 0K
描述: IC FLEXPC CLK PROGR P4 56-SSOP
產(chǎn)品變化通告: Product Discontinuation 19/Jul/2010
標準包裝: 1,000
系列: FlexPC™
類型: 時鐘/頻率發(fā)生器,多路復(fù)用器
PLL:
主要目的: Intel CPU,SATA CPU
輸入: 晶體
輸出: 時鐘
電路數(shù): 1
比率 - 輸入:輸出: 1:20
差分 - 輸入:輸出: 無/是
頻率 - 最大: 400MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 56-BSSOP(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 56-SSOP
包裝: 帶卷 (TR)
其它名稱: CV115FPVG8
COMMERCIALTEMPERATURERANGE
12
IDTCV115F
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
WD HARD ALARM TIMER [7:0]
WD SOFT ALARM TIMER [3:0]
WDE
Trigger Watch Dog Circuit
If Soft Alarm Enabled (byte 27):
Set WDSRB (byte 6)
Load CPU N selection
into CPU PLL
Load SRC N selection
into SRC PLL
If Hard Alarm Enabled (byte 27):
Set WDHRB (byte 6)
Load CPU N and Band selections into CPU PLL
Load SRC N selections into SRC PLL
If Hard Alarm Relatch Enabled:
Latch FSC, B, A
WD SOFT AND HARD ALARM/TIME OUT OPERATION
PLL FREQUENCY PROGRAMMING PROCEDURES
The user changes PLL frequency through Soft Alarm or Hard Alarm. The Watch Dog circuit has to be enabled. Based on their application, the user may
enable either one or both of the alarms.
User presets the CPU PLL N and SRC PLL N value:
1.
Set CPU PLL N, CN1 and CN2, byte 18 and byte 19
2.
Set SRC(PCI Express) PLL N, PN1 and PN2, byte 21, 22
User selects the frequency for Soft Alarm and Hard Alarm, if enabled respectively:
4.
Select Soft Alarm frequency, byte 23
5.
Select Hard Alarm frequency, byte 24
User sets the Timer and enables the WD circuit for frequency switch:
6.
Set Hard Alarm Timer, byte 25
7.
Set Soft Alarm Timer, byte 26
8.
Enable Soft and Hard Alarm, byte 27
9.
Enable Watch Dog (WDE), byte 27
WDE Disable resets WDSRB and WDHRB.
PCI CLK is selectable from SRC PLL or SATA PLL, byte 5 bit 6. If from SRC PLL, PCI frequency = 1/3 of SRC frequency. If from SATA, PCI
is fixed to 3 selections, 33MHz, 36MHz and 40MHz, byte 5 bit[5:4].
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