參數(shù)資料
型號: IDTCV115FPVG8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 7/19頁
文件大?。?/td> 0K
描述: IC FLEXPC CLK PROGR P4 56-SSOP
產(chǎn)品變化通告: Product Discontinuation 19/Jul/2010
標準包裝: 1,000
系列: FlexPC™
類型: 時鐘/頻率發(fā)生器,多路復用器
PLL:
主要目的: Intel CPU,SATA CPU
輸入: 晶體
輸出: 時鐘
電路數(shù): 1
比率 - 輸入:輸出: 1:20
差分 - 輸入:輸出: 無/是
頻率 - 最大: 400MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 56-BSSOP(0.295",7.50mm 寬)
供應商設備封裝: 56-SSOP
包裝: 帶卷 (TR)
其它名稱: CV115FPVG8
COMMERCIALTEMPERATURERANGE
IDTCV115F
PROGRAMMABLEFLEXPC CLOCKFORP4PROCESSOR
15
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
ppm
Static Error(1,2)
See Tperiod Min. - Max. values
0
ppm
TPERIOD
Clock Period(2)
33.33MHz output nominal
29.991
30.009
ns
33.33MHz output spread
29.991
30.1598
VOH
Output HIGH Voltage
IOH = -1mA
2.4
V
VOL
Output LOW Voltage
IOL = 1mA
0.55
V
IOH
Output HIGH Current
VOH at Min. = 1V
-33
mA
VOH at Max. = 3.135V
-33
IOL
Output LOW Current
VOL at Min. = 1.95V
30
mA
VOL at Max. = 0.4V
38
Edge Rate(1)
Rising edge rate
1
4
V/ns
Edge Rate(1)
Fallingedgerate
1
4
V/ns
tR1
Rise Time(1)
VOL = 0.8V, VOH = 2V
0.3
1.2
ns
tF1
FallTime(1)
VOL = 0.8V, VOH = 2V
0.3
1.2
ns
dT1
Duty Cycle(1)
VT = 1.5V
45
55
%
tSK1
Skew(1)
VT = 1.5V
500
ps
tJCYC-CYC
Jitter, Cycle to Cycle(1)
VT = 1.5V
500
ps
ELECTRICAL CHARACTERISTICS - PCICLK / PCICLK_F
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 30pF
NOTES:
1.
This parameter is guaranteed by design, but not 100% production tested.
2.
All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
ELECTRICAL CHARACTERISTICS - CPU, SRC, AND DOT96 0.7 CURRENT MODE
DIFFERENTIAL PAIR, CONTINUED(1)
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 2pF
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
Skew, CPU[1:0](2)
100
tSK3
Skew, CPU2(2)
VT = 50%
250
ps
Skew, SRC(2)
250
Jitter, Cycle to Cycle, CPU[1:0](2)
——
85
tJCYC-CYC
Jitter, Cycle to Cycle, CPU2(2)
Measurement from differential waveform
100
ps
Jitter, Cycle to Cycle, SRC(2)
125
Jitter, Cycle to Cycle, DOT96(2)
250
NOTES:
1.
SRC clock outputs run only at 100MHz.
2.
This parameter is guaranteed by design, but not 100% production tested.
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