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參數(shù)資料
| 型號： | IDTIDT71P71804250BQ |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 18Mb Pipelined DDR⑩II SRAM Burst of 2 |
| 中文描述： | 35.7流水線的DDR II SRAM的突發(fā)⑩2 |
| 文件頁數(shù)： | 10/23頁 |
| 文件大?。?/td> | 241K |
| 代理商： | IDTIDT71P71804250BQ |
6.42
10
IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 2 Commercial Temperature Range
DC Elec tric al Charac teristic s Over the Operating Temperature and
S upply Voltage Range
(V
DD
= 1.8 ± 100mV, V
DDQ
= 1.4V to 1.9V)
Parameter
Symbol
Test Conditions
Mn
Max
Unit
Note
Input Leakage Current
I
IL
V
DD
= Max V
IN
= V
SS
to V
DDQ
-2
+2
μ
A
Output Leakage Current
I
OL
Output Disabled
-2
+2
μ
A
Operating Current
(x36): DDR
I
DD
V
DD
= Max,
I
OUT
= 0mA (outputs open),
Cycle Time > t
KHKH
Min
250MH
Z
-
900
mA
1
200MHz
-
800
167MHz
-
700
Operating Current
(x18): DDR
I
DD
V
DD
= Max,
I
OUT
= 0mA (outputs open),
Cycle Time > t
KHKH
Min
250MH
Z
-
850
mA
1
200MHz
-
750
167MHz
-
650
Standby Current: NOP
I
SB1
Device Deselected (in NOP state),
I
OUT
= 0mA (outputs open),
f=Max,
All Inputs <0.2V or > VDD -0.2V
250MH
Z
-
325
mA
2
200MHz
-
300
167MHz
-
275
Output High Voltage
V
OH1
RQ = 250
,
I
OH
= -15mA
V
DDQ
/2-0.12
V
DDQ
/2+0.12
V
3,7
Output LowVoltage
V
OL1
RQ = 250
,
I
OH
= 15mA
V
DDQ
/2-0.12
V
DDQ
/2+0.12
V
4,7
Output High Voltage
V
OH2
I
OH
= -0.1mA
V
DDQ
-0.2
V
DDQ
V
5
Output LowVoltage
V
OL2
I
OL
= 0.1mA
V
SS
0.2
V
6
6112 tbl 10c
NOTES:
1. Operating Current is measured at 100% bus utilization.
2. Standby Current is only after all pending read and write burst operations are completed.
3. Outputs are impedance-controlled. I
OH
= -(V
DDQ
/2)/(RQ/5) and is guaranteed by device characterization for 175
< RQ < 350
.
This parameter is tested at RQ =
250
,
which gives a nomnal 50
output impedance.
4. Outputs are impedance-controlled. I
OL
= (V
DDQ
/2)/(RQ/5) and is guaranteed by device characterization for 175
< RQ < 350
.
This parameter is tested at RQ =
250
,
which gives a nomnal 50
output impedance.
5. This measurement is taken to ensure that the output has the capability of pulling to the V
DDQ
rail, and is not intended to be used as an impedance measurement point.
6. This measurement is taken to ensure that the output has the capability of pulling to V
ss
, and is not intended to be used as an impedance measurement point.
7. Programmable Impedance Mode.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDTIDT71P79104167BQ | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:18Mb Pipelined DDR⑩II SIO SRAM Burst of 2 |
| IDTIDT71P79104167BQI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:18Mb Pipelined DDR⑩II SIO SRAM Burst of 2 |
| IDTIDT71P79104200BQ | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:18Mb Pipelined DDR⑩II SIO SRAM Burst of 2 |
| IDTIDT71P79104200BQI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:18Mb Pipelined DDR⑩II SIO SRAM Burst of 2 |
| IDTIDT71P79104250BQ | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:18Mb Pipelined DDR⑩II SIO SRAM Burst of 2 |
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