參數資料
型號: IDTIDT71P71804250BQ
廠商: Integrated Device Technology, Inc.
英文描述: 18Mb Pipelined DDR⑩II SRAM Burst of 2
中文描述: 35.7流水線的DDR II SRAM的突發(fā)⑩2
文件頁數: 11/23頁
文件大?。?/td> 241K
代理商: IDTIDT71P71804250BQ
6.42
11
IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 2 Commercial Temperature Range
Input Elec tric al Charac teristic s Over the Operating Temperature and
S upply Voltage Range
(V
DD
= 1.8 ± 100mV, V
DDQ
= 1.4V to 1.9V)
NOTES:
1. These are DC test criteria. DC design criteria is V
REF
+ 50mV. The AC V
IH
/V
IL
levels are defined separately for measuring timng parameters.
2. V
IL
(Mn) DC = -0.3V, V
IL
(Mn) AC = -0.5V (pulse width <20% tKHKH (mn))
3. V
IH
(Max) DC = V
DDQ
+0.3, V
IH
(Max) AC = V
DD
+0.5V (pulse width <20% tKHKH (mn))
4. This conditon is for AC function test only, not for AC parameter test.
5. To maintain a valid level, the transitioning edge of the input must:
a) Sustain a constant slew rate fromthe current AC level through the target AC level, V
IL
(AC) or V
IH
(AC)
b) Reach at leaset the target AC level.
c) After the AC target level is reached, continue to maintain at least the target DC level, V
IL
(DC) or V
IH
(DC)
V
IL
V
DD
V
DD
+0.25
V
DD
+0.5
20%tKHKH(MIN)
6112drw21
V
SS
V
IH
V
SS
-0.25V
V
SS
-0.5V
20% tKHKH(MIN)
6112drw22
Overshoot Timing
Undershoot Timing
PARAMETER
SYMBOL
MIN
MAX
UNIT
NOTES
Input High Voltage, DC
V
IH
(DC
)
V
REF
+0.1
V
DDQ
+0.3
V
1,2
Input LowVoltage, DC
V
IL
(DC)
-0.3
V
REF
-0.1
V
1,3
Input High Voltage, AC
V
IH
(AC)
V
REF
+0.2
-
V
4,5
Input LowVoltage, AC
V
IL
(AC)
-
V
REF
-0.2
V
4,5
6112 tbl 10d
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