參數(shù)資料
型號(hào)： IDTIDT71P79804267BQI
廠商： Integrated Device Technology, Inc.
英文描述： 18Mb Pipelined DDR⑩II SIO SRAM Burst of 2
中文描述： 35.7流水線⑩二二氧化硅的DDR SRAM的爆裂2
文件頁(yè)數(shù)： 12/23頁(yè)
文件大?。?/td> 641K
代理商： IDTIDT71P79804267BQI
6.42
12
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2 Commercial and Industrial Temperature Ranges
Input Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range
(V
DD
= 1.8 ± 100mV, V
DDQ
= 1.4V to 1.9V)
Parameter
Symbol
Mn
Max
Unit
Notes
Input High Voltage, DC
V
IH
(DC
)
V
REF
+0.1
V
DDQ
+0.3
V
1,2
Input LowVoltage, DC
V
IL
(DC)
-0.3
V
REF
-0.1
V
1,3
Input High Voltage, AC
V
IH
(AC)
V
REF
+0.2
-
V
4,5
Input LowVoltage, AC
V
IL
(AC)
-
V
REF
-0.2
V
4,5
6432 tbl 10d
NOTES:
1. These are DC test criteria. DC design criteria is VREF + 50mV. The AC VIH/VIL levels are defined separately for measuring timng
parameters.
2. VIH (Max) DC = VDDQ+0.3, VIH (Max) AC = VDD +0.5V (pulse width <20% tKHKH (mn))
3. VIL (Mn) DC = -0.3V, VIL (Mn) AC = -0.5V (pulse width <20% tKHKH (mn))
4. This conditon is for AC function test only, not for AC parameter test.
5. To maintain a valid level, the transitioning edge of the input must:
a) Sustain a constant slew rate fromthe current AC level through the target AC level, VIL(AC) or VIH(AC)
b) Reach at least the target AC level.
c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC)
V
IL
V
DD
V
DD
+0.25
V
DD
+0.5
20%tKHKH(MIN)
6432drw21
V
SS
V
IH
V
SS
-0.25V
V
SS
-0.5V
20% tKHKH(MIN)
6432drw22
Overshoot Timing
Undershoot Timing
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