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| 型號(hào)： | IMST400 |
| 文件頁(yè)數(shù)： | 24/74頁(yè) |
| 文件大?。?/td> | 563K |
| 代理商： | IMST400 |
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IMS T400
/ 74
24
ProcClockOut
MemnotWrD0
MemnotRfD1
MemAD2–31
notMemWrB0–3
(Early write)
notMemS0
(CE)
notMemS1
(ALE)
T1
T2
T3
Tmx
T5
T6
T1
Tstate
TaVS0LTS0LaX
TWrHDX
TdVWrH
Data
Address
TS0LWrL
TWrLWrH
TS0HWrH
TS0LS0H
TS0LS1L
TS0LS1H
TS0HS1H
T4
Data
Data
notMemWrB0–3
(Late write)
TS0LWrL
TWrLWrH
9
5
1
Figure 5.8
IMS T400 external write cycle
5.4
Wait
Taking
MemWait
high with the timing shown (figure 5.9) will extend the duration of
T4
.
MemWait
is
sampled close to the falling edge of
ProcClockOut
during a
T3
or
T4
period, prior to, but not at the end
of
T4
. By convention,
notMemS4
is used to synchronize wait state insertion. If this or another strobe is
used, its delay should be such as to take the strobe low an even number of periods
Tm
after the start of
T1
, to coincide with a rising edge of
ProcClockOut
.
MemWait
may be kepthigh indefinitely, although ifdynamic memory refresh is used itshould notbe kept
high longenough to interfere with refresh timing.
MemWait
operates normallyduring all cycles,including
refresh and configuration cycles. It does not affect internal memory access in any way.
If thestartof
T5
wouldcoincidewitha fallingedgeof
ProcClockOut
an extrawait period
Tm
(
EW
)isgener-
atedbytheEMItoforcecoincidencewitharisingedge.Risingedgecoincidenceisonlyforcedifwaitstates
are added, otherwise coincidence with a falling edge is permitted.
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| IMST414B-G15S | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Peripheral IC |
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