![](http://datasheet.mmic.net.cn/230000/IMST400_datasheet_15584548/IMST400_4.png)
IMS T400
/ 74
4
The IMS T400 can directly access a linearaddress space of 4 Gbytes. The 32 bit wide memory interface
uses multiplexeddata and addresslines andprovides adata rate ofupto 4 bytes every150 nanoseconds
(26.6 Mbytes/sec)for a 20 MHz device. Aconfigurable memory controller provides all timing, control and
DRAM refresh signals for a wide variety of mixed memory systems.
System Services include processor reset and bootstrap control, together with facilities for error analysis.
Error signals may be daisy-chained in multi-transputer systems.
The standard INMOS communicationlinks allownetworks oftransputer familyproductsto be constructed
by directpoint topoint connectionswithno externallogic.TheIMS T400links supportthestandardoperat-
ing speedof10 Mbits/sec,but alsooperate at 5or 20Mbits/sec. Eachlinkcantransferdatabi-directionally
at up to 2.35 Mbytes/sec.
The IMS T400-20 is pin compatible with the IMS T805-20 and IMS T425-20 and can be plugged directly
into a circuit designed for those devices.
The transputer is designed to efficiently implement high level languages such as ANSI C and
occam
.
Access to the transputer at machine level is seldom required, but if necessaryrefer to the TransputerIn-
struction Set – A Compiler Writer’s Guide