- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360859 > IMST425-X25S 32-Bit Microprocessor PDF資料下載
參數(shù)資料
| 型號： | IMST425-X25S |
| 元件分類： | 32位微控制器 |
| 英文描述： | 32-Bit Microprocessor |
| 中文描述： | 32位微處理器 |
| 文件頁數(shù)： | 15/74頁 |
| 文件大?。?/td> | 563K |
| 代理商： | IMST425-X25S |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁
5 External memory interface
/ 74
15
5.1
Pin functions
5.1.1
MemAD2–31
External memoryaddresses anddata are multiplexedonone bus. Onlythetop 30bitsof addressare out-
put on the external memory interface, using pins
MemAD2-31
. They are normally output only during
Tstates T1
and
T2
, and should be latched during this time. The data bus is 32 bits wide. It uses
Me-
mAD2-31
for the top 30 bits and
MemnotRfD1
and
MemnotWrD0
for the lower two bits.
5.1.2
notMemRd
For a read cycle the read strobe
notMemRd
is low during
T4
and
T5
. Data is read by the transputer on
the rising edge of this strobe, and may beremoved immediately afterward. Ifthe strobeduration is insuffi-
cient it may be extended by adding extra periods
Tm
to either or both of the
Tstates T4
and
T5
. Further
extension may be obtained by inserting wait states at the end of
T4
.
5.1.3
MemnotWrD0
During
T1
and
T2
this pin will be low if the cycle is a writecycle, otherwise it will be high. During
Tstates
T3
to
T6
it becomes bit 0 of the data bus. In both cases it follows the general timing of
MemAD2-31
.
5.1.4
notMemWrB0–3
Because the transputer uses word addressing, four write strobes are provided; one to write each byte of
the word.
notMemWrB0
addresses the least significant byte.
5.1.5
notMemS0–4
Tofacilitate controlof differenttypes of memoryand devices, theEMI is providedwith five strobe outputs,
four of whichcanbe configured bytheuser.The strobesare conventionallyassignedthe functions shown
in the read and write cycle diagrams, although there is no compulsion to retain these designations.
5.1.6
MemWait
Waitstates can be selected by taking
MemWait
high. Externally generated wait states can be added to
extend the duration of
T4
indefinitely.
5.1.7
MemnotRfD1
During
T1
and
T2
, this pin is lowif the address on
MemAD2-31
is a refresh address, otherwise it is high.
During
Tstates T3
to
T6
it becomesbit 1 of the data bus.In bothcases it followsthe general timing of
Me-
mAD2-31
.
5.1.8
notMemRf
The IMS T400 can be operated with memory refresh enabled or disabled. The selection is made during
memory configuration, when the refresh interval is also determined.
5.1.9
RefreshPending
When high, this pin signals that a refresh cycle is pending.
相關PDF資料 |
PDF描述 |
|---|---|
| IMST800C-G17S | Peripheral IC |
| IMST800C-G20S | Peripheral IC |
| IMST800C-G30S | Peripheral IC |
| IMST805-F20E | 32-Bit Microprocessor |
| IMST805-F25S | 32-Bit Microprocessor |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IMST800C-G17S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| IMST800C-G20S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| IMST800C-G30S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| IMST801 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:IMST801 TRANSPUETR |
| IMST801-G20M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:IMST801 TRANSPUETR |
發(fā)布緊急采購，3分鐘左右您將得到回復。