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參數(shù)資料
| 型號(hào)： | IMST425-X25S |
| 元件分類： | 32位微控制器 |
| 英文描述： | 32-Bit Microprocessor |
| 中文描述： | 32位微處理器 |
| 文件頁數(shù)： | 29/74頁 |
| 文件大?。?/td> | 563K |
| 代理商： | IMST425-X25S |
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5 External memory interface
/ 74
29
5.6
Direct memory access
Direct memory access (DMA) can be requested at any time by taking the asynchronous
MemReq
input
high. The transputer samples
MemReq
just before falling edges of
ProcClockOut
. To guarantee taking
over the bus immediately followingeither a refresh or externalmemory cycle,
MemReq
must besampled
at least four periods
Tm
before the end of
T6
. In the absence of an external memory cycle, the address
bus is tristated two periods
Tm
after the
ProcClockOut
rising edge which follows the sample.
Removalof
MemReq
is sampledjustbeforefallingedgesof
ProcClockOut
and
MemGranted
isremoved
synchronouslywith thesecondfallingedgeof
ProcClockOut
which followsthesample. If accuratetiming
of DMA is required, the setup time relative to
ProcClockOut
must be met. Further external bus activity,
eitherrefresh,external cyclesorreflectionofinternal cycles,willcommenceatthenextbutone risingedge
of
ProcClockOut
.
Thestrobes(
notMemS0–4
and
notMemWrB0–3
)areleftintheirinactivestatesduringDMA.DMAcannot
interrupt a refresh or external memory cycle, and outstanding refresh cycles will occur before the bus is
released to DMA. DMA does not interfere with internal memory cycles in any way, although a program
runningininternalmemory wouldhavetowaitfor theendof DMAbeforeaccessingexternalmemory.DMA
cannot accessinternalmemory.If DMAextendslonger thanone refreshinterval(MemoryRefreshConfig-
uration Coding, table 5.11), the DMA user becomes responsible for refresh (see section 5.5). DMA may
also inhibit an internally running program from accessing external memory.
DMA allows a bootstrap program to be loaded intoexternal RAM ready for execution after reset. If
Mem-
Req
is held high throughout reset,
MemGranted
will be asserted before the bootstrap sequence begins.
MemReq
must be high at least one period
TDCLDCL
of
ClockIn
before
Reset
. The circuit shouldbe de-
signed to ensure correct operation if
Reset
could interrupt a normal DMA cycle.
T400-20
Min
3
96
4
50
0
0
Symbol
TMRHPCL
TPCLMGH
TMRLPCL
TPCLMGL
TADZMGH
TMGLADV
Notes
1 Setup time need only be met to guarantee sampling on this edge.
2 If an external cycle is active, maximum time could be
(1 EMI cycle
Tmx
)+(1 refresh cycle
TRfLRfH
)+(6 periods
Tm
).
Table 5.8
Parameter
MemReq
setup before
ProcClockOut
falling
MemReq
response time
Memreq
removal before
ProcClockOut
falling
MemReq
end response time
Bus tristate before
MemGranted
Bus active after end of
MemGranted
Max
14
110
16
66
27
32
Units
ns
ns
Note
1
2
ns
ns
ns
Memory request
ProcClockOut
T6
MemReq
MemGranted
MemnotRfD1
MemAD2–31
MemnotWrD0
TPCLMGH
TPCLMGL
TMGLADV
TADZMGH
TMRHPCL
TMRLPCL
Figure 5.13
IMS T400 memory request timing
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