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參數(shù)資料
| 型號： | Intel387 dx |
| 廠商： | Intel Corp. |
| 英文描述： | DX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器) |
| 中文描述： | 霉素?cái)?shù)學(xué)協(xié)處理器（32位數(shù)學(xué)協(xié)處理器） |
| 文件頁數(shù)： | 26/41頁 |
| 文件大小： | 406K |
| 代理商： | INTEL387 DX |
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Intel387
TM
DX MATH COPROCESSOR
The READYO
Y
output of the Intel387 DX MCP indi-
cates when a bus cycle for the MCP may be termi-
nated if no extra wait states are required. For all
write cycles (except those for the instructions
FLDENV and FRSTOR), READYO
Y
is always as-
serted in the first T
RS
state, regardless of the num-
ber of wait states. For all read cycles and write cy-
cles for FLDENV and FRSTOR, READYO
Y
is al-
ways asserted in the second T
RS
state, regardless
of the number of wait states. These rules apply to
both pipelined and nonpipelined cycles. Systems de-
signers must use READYO
Y
in one of the following
ways:
1. Connect it (directly or through logic that ORs
READY signals from other devices) to the
READY
Y
inputs of the Intel386 DX CPU and In-
tel387 DX MCP.
2. Use it as one input to a wait-state generator.
The following sections illustrate different types of
MCP bus cycles.
Because
amounts of overhead before, between, and after op-
erand transfer cycles, it is not possible to represent
in a few diagrams all of the combinations of succes-
sive operand transfer cycles. The following bus-cy-
cle diagrams show memory cycles between MCP
operand-transfer cycles. Note however that, during
the instructions FLDENV, FSTENV, FSAVE, and
FRSTOR, some consecutive accesses to the MCP
do not have intervening memory accesses. For the
timing relationship between operand transfer cycles
and opcode write or other overhead activities, see
Figure 3.8.
different
instructions
have
different
3.4.1 NONPIPELINED BUS CYCLES
Figure 3.5 illustrates bus activity for consecutive
nonpipelined bus cycles.
3.4.1.1 Write Cycle
At the second clock of the bus cycle, the Intel387
DX MCP enters the T
RS
(READY
Y
-sensitive) state.
During this state, the Intel387 DX MCP samples the
READY
Y
input and stays in this state as long as
READY
Y
is inactive.
In write cycles, the MCP drives the READYO
Y
sig-
nal for one CLK period beginning with the second
CLK of the bus cycle; therefore, the fastest write
cycle takes two CLK cycles (see cycle 2 of Figure
3.5). For the instructions FLDENV and FRSTOR,
however, the MCP forces a wait state by delaying
the activation of READYO
Y
to the second T
RS
cy-
cle (not shown in Figure 3.5).
When READY
Y
is asserted the MCP returns to the
idle state, in which ADS
Y
could be asserted again
by the Intel386 DX Microprocessor for the next cy-
cle.
3.4.1.2 Read Cycle
At the second clock of the bus cycle, the MCP en-
ters the T
RS
state. See Figure 3.5. In this state, the
MCP samples the READY
Y
input and stays in this
state as long as READY
Y
is inactive.
At the rising edge of CLK in the second clock period
of the cycle, the MCP starts to drive the D31–D0
outputs and continues to drive them as long as it
stays in T
RS
state.
In read cycles that address the MCP, at least one
wait state must be inserted to insure that the In-
tel386 DX CPU latches the correct data. Since the
MCP starts driving the system data bus only at the
rising edge of CLK in the second clock period of the
bus cycle, not enough time is left for the data signals
to propagate and be latched by the Intel386 DX CPU
at the falling edge of the same clock period. The
MCP drives the READYO
Y
signal for one CLK peri-
od in the third CLK of the bus cycle. Therefore, if the
READYO
Y
output is used to drive the Intel386 DX
CPU READY
Y
input, one wait state is inserted auto-
matically.
Because one wait state is required for MCP reads,
the minimum is three CLK cycles per read, as cycle
3 of Figure 3.5 shows.
When READY
Y
is asserted the MCP returns to the
idle state, in which ADS
Y
could be asserted again
by the Intel386 DX CPU for the next cycle. The tran-
sition from T
RS
state to idle state causes the MCP to
put the tristate D31–D0 outputs into the floating
state, allowing another device to drive the system
data bus.
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PDF描述 |
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| Intel387 sx | SX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器) |
| INTEL486 GX | Emedded Ultra-Low Power INTEL486 GX Processor(嵌入式超低能量處理器) |
| INTEL486 SX | Emedded Ultra-Low Power INTEL486 SX Processor(嵌入式超低能量處理器) |
| INTEL82801 | 82801AB (ICH0) I/O Controller Hub |
| INTEL82802AB | Firmware Hub (FWH) |
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| INTEL387SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR |
| INTEL387TMDX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR |
| INTEL740 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Graphics (GUI) Accelerator |
| INTEL82801 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:82801AB (ICH0) I/O Controller Hub |
| INTEL82802AB | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Firmware Hub (FWH) |
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