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參數(shù)資料
| 型號： | INTEL486 SX |
| 廠商： | Intel Corp. |
| 英文描述： | Emedded Ultra-Low Power INTEL486 SX Processor(嵌入式超低能量處理器) |
| 中文描述： | Emedded超低功耗英特爾486山西處理器（嵌入式超低能量處理器） |
| 文件頁數(shù)： | 6/38頁 |
| 文件大小： | 346K |
| 代理商： | INTEL486 SX |
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2
Embedded Ultra-Low Power Intel486 SX Processor
Auto HALT Power Down —
After the execution of
a HALT instruction, the embedded ULP Intel486
SX processor issues a normal Halt bus cycle and
the clock input to the processor core is automati-
cally stopped, causing the processor to enter the
Auto HALT Power Down state (40–85 mW typical,
depending on input clock frequency).
The embedded ULP Intel486 SX processor differs
from the Intel486 SX processor in the following
areas:
Processor Upgrade Removed —
The UP# signal
is not provided.
Parity Signals Removed
— The DP3-DP0 and
PCHK# signals are not provided.
Separate Processor-Core Power
— While the
embedded ULP Intel486 SX processor requires a
supply voltage of 3.3 V, the processor core has
dedicated V
pins and operates with a supply
voltage as low as 2.4 V.
Small, Low-Profile Package
— The 176-Lead
Thin Quad Flat Pack (TQFP) package is approxi-
mately 26 mm square and only 1.5 mm in height.
This is approximately the diameter and thickness
of a U.S. quarter. The embedded ULP Intel486 SX
processor is ideal for embedded hand-held and
battery-powered applications.
Level Keeper Circuits
— The embedded ULP
Intel486 SX processor has level-keeper circuits for
its 32-bit external data bus signals. They retain
valid high and low logic voltage levels when the
processor is in the Stop Grant and Stop Clock
states. This is a power-saving improvement from
the floating data bus of the Intel486 SX processor.
Auto Clock Freeze
— The embedded ULP
Intel486 SX processor monitors bus events and
internal activity. The Auto Clock Freeze feature
automatically controls internal clock distribution,
turning off clocks to internal units when they are
idle. This power-saving function is transparent to
the embedded system.
Fast Clock Restart
— The embedded ULP
Intel486 SX processor requires only eight clock
periods to synchronize its internal clock with the
CLK input signal. This provides for faster transition
from the Stop Clock State to the Normal State. For
33-MHz operation, this synchronization time is
only 240 ns compared with 1 ms (PLL startup
latency) for the Intel486 processor.
1.2
Family Members
Table 1 shows the embedded ULP Intel486 SX
processor and briefly describes its characteristics.
Table 1. The Embedded Ultra-Low Power Intel486
SX Processor
Product
Supply
Voltage
(V
CCP
)
Processor
Core Supply
Voltage
(V
CC
)
2.4 V to 3.3 V
Processor
Frequency
(MHz)
Package
FA80486SXSF-33
3.3 V
25
176-Lead
TQFP
2.7 V to 3.3 V
33
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