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參數(shù)資料
| 型號(hào)： | IP113 |
| 英文描述： | 10/100Base-T to 100Base-FX Converter |
| 中文描述： | 10/100至100Base - FX光纖轉(zhuǎn)換器 |
| 文件頁數(shù)： | 1/27頁 |
| 文件大?。?/td> | 186K |
| 代理商： | IP113 |
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IP113
10/100 Base-Tx / Fx Converter
Feature
Preliminary, Specification subject to change without notice
IP113-DS-P07
Jul.19, 2002
1
2 port 10/100 Ethernet switch with built in transceivers
and memory
Build in SSRAM for frame buffer
Built in storage of 1K MAC address
Support flow control
-
Support IEEE802.3x for flow control on full duplex
mode operation
-
Support back pressure for flow control in half duplex
mode operation
A 2 port switching fabric
-
Support two-level hashing algorithm to solve address
collision
-
Support address aging
-
Store and forward mode
-
Broadcast storm protection
-
Full line speed capability of 148800 (14880)
packets/sec for 100M (10M)
Integrate two transceivers
-
TP port with auto negotiation
-
Fully digital adaptive equalizer and timing recovery
module
-
Base line Wander correction
-
10BaseTX, 100BaseTX, and 100BaseFX operation
Support link fault pass through
TP port forced 10M/100M, full/half
Support all pass function - hashing disabled
LED status of Link, activity, Full/half duplex, and speed
Initial parameter setting by pin configuration or
EEPROM
Utilize single clock source only (25Mhz)
Utilize single power (2.5v)
0.25um technology
Packaged in 128 pin PQFP
General Description
IP113 is a 2 port 10/100 Ethernet integrated switch. It
consists of a 2-port switch controller and two Fast
Ethernet transceivers. Each of the transceivers complies
with the IEEE802.3, IEEE802.3u, and IEEE802.3x
specifications. The transceivers in IP113 are designed in
DSP approach with advance 0.25um technology; this
results in high noise immunity and robust performance.
The IP113 operates in store and forward mode. It stores
the incoming packet to the internal SSRAM and learns
the SA (source address) automatically if the packet is
error free. The SA is stored in the internal address table.
IP113 forwards a packet according to DA destination
address and address table. When the segments of
destination ports are free, it reads the packet from the
internal SSRAM and forwards it to the appropriate ports
according to the address table. The incoming packets
with errors are dropped. IP113 supports IEEE802.3x,
optional backpressure, and various LED functions, etc.
These functions can be configured to fit the different
requirements by feeding operation parameters via
EEPROM interface or pull up/down resistors on specified
pins.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IP113M | Managed 10/100Base-TX / FX Media Converter |
| IP117AK-BSS2 | Voltage Regulator |
| IP117AK-DESC | Voltage Regulator |
| IP117AR | Voltage Regulator |
| IP117AR-883B | Voltage Regulator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IP113ALF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10 /100Base-Tx/Fx Media Converter |
| IP113ALF-DS-R01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10 /100Base-Tx/Fx Media Converter |
| IP113ALF-DS-R02 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10 /100Base-Tx/Fx Media Converter |
| IP113ALF-DS-R03 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10 /100Base-Tx/Fx Media Converter |
| IP113ALF-DS-R04 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10 /100Base-Tx/Fx Media Converter |
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