參數(shù)資料
型號: IP80C88
廠商: Intersil
文件頁數(shù): 16/38頁
文件大?。?/td> 0K
描述: IC CPU 8/16BIT 5V 5MHZ 40-DIP
標(biāo)準(zhǔn)包裝: 99
處理器類型: 80C88 8/16-位
速度: 5MHz
電壓: 4.5 ~ 5.5V
安裝類型: 通孔
封裝/外殼: 40-DIP(0.600",15.24mm)
供應(yīng)商設(shè)備封裝: 40-DIP
包裝: 管件
23
FN2949.4
February 22, 2008
Waveforms
FIGURE 11. BUS TIMING - MAXIMUM MODE (USING 82C88)
NOTES:
8. RDY is sampled near the end of T2, T3, TW to determine if TW machine states are to be inserted.
9. Signals at 82C84A or 82C88 are shown for reference only.
10. Status inactive in state just prior to T4.
11. The issuance of the 82C88 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA, and DEN) lags the active high
82C88 CEN.
T1
T2
T3
T4
TCLCL
TCH1CH2
TCL2CL1 TW
TCHCL (3)
(21) TCHSV
(SEE NOTE 20)
TCLDV
TCLAX
(23) TCLAV
TCLAV
A19-A16
TSVLH
TCLLH
TR1VCL
TCHLL
TCLR1X
TCLAV
TDVCL
TCLDX1
TCLAX
AD7-AD0
DATA IN
TRYHSH
(39) TCLRH
TRHAV
(41) TCHDTL
TCLRL
TRLRH
TCHDTH
(37) TAZRL
TCLML
TCLMH
(35) TCVNV
TCVNX
CLK
QS0, QS1
S2, S1, S0 (EXCEPT HALT)
A19/S6-A16/S3
ALE (82C88 OUTPUT)
RDY (82C84 INPUT)
NOTES 18, 19
READY 80C86 INPUT)
READ CYCLE
82C88
OUTPUTS
SEE NOTES 19, 21
MRDC OR IORC
DEN
S6-S3
AD7-AD0
RD
DT/R
TCLAV
(1)
(4)
(23)
TCLCH
(2)
TCLSH
(22)
(24)
(23)
(27)
(29)
(31)
(8)
(9)
TCHRYX
(11)
(20)
(12) TRYLCL
(24)
TRYHCH
(10)
(6)
(7)
(23)
(40)
(42)
(45)
(38)
(18)
(19)
(36)
(33)
TCLAZ
(25)
(5)
A15-A8
80C88
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