- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4069 > IP80C88 (Intersil)IC CPU 8/16BIT 5V 5MHZ 40-DIP PDF資料下載
參數(shù)資料
| 型號： | IP80C88 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 4/38頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CPU 8/16BIT 5V 5MHZ 40-DIP |
| 標(biāo)準(zhǔn)包裝： | 99 |
| 處理器類型： | 80C88 8/16-位 |
| 速度： | 5MHz |
| 電壓： | 4.5 ~ 5.5V |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 40-DIP（0.600"，15.24mm） |
| 供應(yīng)商設(shè)備封裝： | 40-DIP |
| 包裝： | 管件 |
第1頁第2頁第3頁當(dāng)前第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁
12
FN2949.4
February 22, 2008
Designers familiar with the 8085 or upgrading an 8085
design should note that the 8085 addresses I/O with an 8-bit
address on both halves of the 16-bit address bus. The
80C88 uses a full 16-bit address on its lower 16 address
lines.
External Interface
Processor Reset and Initialization
Processor initialization or start up is accomplished with
activation (HIGH) of the RESET pin. The 80C88 RESET is
required to be HIGH for greater than four clock cycles. The
80C88 will terminate operations on the high-going edge of
RESET and will remain dormant as long as RESET is HIGH.
The low-going transition of RESET triggers an internal reset
sequence for approximately 7 clock cycles. After this interval
the 80C88 operates normally, beginning with the instruction
in absolute location FFFFOH (see Figure 2). The RESET
input is internally synchronized to the processor clock. At
initialization, the HIGH to LOW transition of RESET must
occur no sooner than 50
μs after power up, to allow complete
initialization of the 80C88.
NMI will not be recognized if asserted prior to the second
CLK cycle following the end of RESET.
Bus Hold Circuitry
To avoid high current conditions caused by floating inputs to
CMOS devices and to eliminate the need for pull-up/down
resistors, “bus-hold” circuitry has been used on 80C88 pins
circuits maintain a valid logic state if no driving source is
present (i.e., an unconnected pin or a driving source which
goes to a high impedance state).
To override the “bus hold” circuits, an external driver must be
capable of supplying 400
μA minimum sink or source current
at valid input voltage levels. Since this “bus hold” circuitry is
active and not a “resistive” type element, the associated
power supply current is negligible. Power dissipation is
significantly reduced when compared to the use of passive
pull-up resistors.
Interrupt Operations
Interrupt operations fall into two classes: software or
hardware initiated. The software initiated interrupts and
software aspects of hardware interrupts are specified in the
instruction set description. Hardware interrupts can be
classified as nonmusical or maskable.
Interrupts result in a transfer of control to a new program
location. A 256 element table containing address pointers to
the interrupt service program locations resides in absolute
locations 0 through 3FFH (see Figure 2), which are reserved
for this purpose. Each element in the table is 4-bytes in size
and corresponds to an interrupt “type”. An interrupting
device supplies an 8-bit type number, during the interrupt
acknowledge sequence, which is used to vector through the
appropriate element to the new interrupt service program
location.
Non-Maskable Interrupt (NMI)
The processor provides a single non-maskable interrupt
(NMI) pin which has higher priority than the maskable
interrupt request (INTR) pin. A typical use would be to
activate a power failure routine. The NMI is edge-triggered
on a LOW to High transition. The activation of this pin
causes a type 2 interrupt.
NMI is required to have a duration in the HIGH state of
greater than two clock cycles, but is not required to be
synchronized to the clock. An high going transition of NMI is
latched on-chip and will be serviced at the end of the current
instruction or between whole moves (2-bytes in the case of
word moves) of a block type instruction. Worst case
response to NMI would be for multiply, divide, and variable
shift instructions. There is no specification on the occurrence
of the low-going edge; it may occur before, during, or after
the servicing of NMI. Another high-going edge triggers
another response if it occurs after the start of the NMI
procedure.
The signal must be free of logical spikes in general and be
free of bounces on the low-going edge to avoid triggering
extraneous responses.
Maskable Interrupt (INTR)
The 80C88 provides a singe interrupt request input (INTR)
which can be masked internally by software with the
resetting of the interrupt enable (IF) flag bit. The interrupt
request signal is level triggered. It is internally synchronized
during each clock cycle on the high-going edge of CLK.
FIGURE 6A. BUS HOLD CIRCUITRY PINS 2-16 AND 35-39
FIGURE 6B. BUS HOLD CIRCUITRY PINS 26-32 AND 34
FIGURE 6.
OUTPUT
DRIVER
INPUT
BUFFER
INPUT
PROTECTION
CIRCUITRY
BOND
PAD
EXTERNAL
PIN
OUTPUT
DRIVER
INPUT
BUFFER
INPUT
PROTECTION
CIRCUITRY
BOND
PAD
EXTERNAL
PIN
P
VCC
80C88
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SPC5200CBV400B | IC MPU 32BIT 500MHZ 272PBGA |
| ABB85DHBR | CONN EDGECARD 170PS R/A .050 SLD |
| XF2M-2215-1A | CONN FPC 22POS 0.5MM PITCH SMD |
| MPC859TCVR100A | IC MPU POWERQUICC 100MHZ 357PBGA |
| FMC25DRES | CONN EDGECARD 50POS .100 EYELET |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IP80C88/+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Microprocessor |
| IP80C88-2 | 功能描述:微處理器 - MPU CPU 8/16BIT 5V 8MHZ IND RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| IP80C88-2/+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Microprocessor |
| IP80C88-2S2064 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| IP80C88S2064 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。