參數(shù)資料
型號: IR3082M
廠商: International Rectifier
英文描述: XPHASE AMD OPTERON/ATHLON 64 CONTROL IC
中文描述: XPHASE AMD皓龍/速龍64控制IC
文件頁數(shù): 7/33頁
文件大?。?/td> 444K
代理商: IR3082M
IR3082
Page 7 of 7
12/17/04
PWM Control Method
The PWM block diagram of the
XPhase
TM
architecture is shown in Figure 3. Feed-forward voltage mode control with
trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the Control IC is used
for the voltage control loop. An external RC circuit connected to the input voltage and ground is used to program the
slope of the PWM ramp and to provide the feed-forward control at each phase. The PWM ramp slope will change
with the input voltage and automatically compensate for changes in the input voltage. The input voltage can change
due to variations in the silver box output voltage or due to drops in the PCB related to changes in load current.
PWM
COMPARATOR
SHARE
ADJUST
ERROR
AMP
RPHS1
RVFB
+
-
+
-
CSCOMP
RPHS2
+
-
+
-
RPHS2
+
-
CPWMRMP
X 0.9
+
-
CPWMRMP
+
-
X 0.9
RPHS1
+
-
+
-
+
-
RCS
RPWMRMP
+
-
CCS
RCS
+
-
CCS
10K
+
-
RDRP
+
-
CSCOMP
+
-
VOUT
GND
RPWMRMP
VBIAS
VDAC
BIASIN
PWMRMP
DACIN
VOSNS+
VOSNS-
RAMPIN+
RAMPIN-
ISHARE
VOSNS-
VDRP
IIN
SCOMP
GATEH
EAIN
GATEL
CSIN+
CSIN-
RMPOUT
EAOUT
FB
VIN
BIASIN
PWMRMP
DACIN
RAMPIN+
RAMPIN-
ISHARE
SCOMP
GATEH
EAIN
GATEL
CSIN+
CSIN-
20mV
IROSC
PWM
COMPARATOR
+
+
SYSTEM
REFERENCE
VOLTAGE
CLOCK
PULSE
GENERATOR
ENABLE
RAMP
DISCHARGE
CLAMP
BODY
BRAKING
COMPARATOR
CURRENT
SENSE
AMPLIFIER
PWM
LATCH
DOMINANT
RESET
S
R
X34
PHASE IC
+
-
+
+
SYSTEM
REFERENCE
VOLTAGE
VBIAS
REGULATOR
CLOCK
PULSE
GENERATOR
ENABLE
RAMP
DISCHARGE
CLAMP
BODY
BRAKING
COMPARATOR
VDAC
VDRP
AMP
IFB
VPEAK
VVALLEY
RAMP GENERATOR
50%
DUTY
CYCLE
CURRENT
SENSE
AMPLIFIER
PWM
LATCH
DOMINANT
RESET
RAMP
SLOPE
ADJUST
S
R
X34
ERROR
AMP
CONTROL IC
COUT
SHARE
ADJUST
ERROR
AMP
+
-
10K
20mV
+
-
PHASE IC
RAMP
SLOPE
ADJUST
Figure 3 – IR3082 PWM Block Diagram
Frequency and Phase Timing Control
The oscillator is located in the Control IC and its frequency is programmable from 150kHz to 1MHZ by an external
resistor. The output of the oscillator is a 50% duty cycle triangle waveform with peak and valley voltages of
approximately 5V and 1V. This signal is used to program both the switching frequency and phase timing of the
Phase ICs. The Phase IC is programmed by resistor divider RRAMP1 and RRAMP2 connected between the VBIAS
reference voltage and the Phase IC LGND pin. A comparator in the Phase ICs detects the crossing of the oscillator
waveform with the voltage generated by the resistor divider and triggers a clock pulse that starts the PWM cycle.
The peak and valley voltages track the VBIAS voltage reducing potential Phase IC timing errors. Figure 4 shows the
Phase timing for an 8 phase converter. Note that both slopes of the triangle waveform can be used for
synchronization by swapping the RAMP+ and RAMP- pins, as shown in Figure 3.
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