參數(shù)資料
型號: IRG4PH40SD
廠商: International Rectifier
英文描述: Fit Rate / Equivalent Device Hours
中文描述: FIT率/等效器件小時
文件頁數(shù): 28/35頁
文件大?。?/td> 112K
代理商: IRG4PH40SD
POWER CYCLING (P/C) Unbiased
Test circuit
Conditions
Bias
Temperature
Duration
Test points
Set to give
T = 100°C
Tj =
100°C
10000 Cycles
2500, 5000, 7500, 10000 Nominal
D
DC
BIAS
Input
Bias
D
= Diode for CoPack devices only
Purpose
Failure Modes
Sensitive Parameters
I
CES
, V
(BR)CES
,
R
θ
JC
,
V
CE(on)
The purpose of Power Cycling is to simulate the thermal and current pulsing
stresses which devices will encounter in actual circuit applications when either the
equipment is turned on and off or power is applied to the device in short bursts
interspersed with quiescent, low power periods. The simulation is achieved by the
on/off application of power to each device while they are in the active linear
region.
The primary failure mode for power cycling is a thermal fatigue of the
silicon/metal interfaces and metal/metal interfaces.
thermomechanical stresses from the heating and cooling, will cause electrical or
thermal performance or degrade.
The fatigue, due to the
If the degradation occurs at the header/die interface, then the thermal impedance
R
θ
JC
, will begin to increase well before any electrical effect is seen. If the
degradation occurs at the wire bond/die interface or the wire bond/post interface,
then on resistance,
V
CE(on)
, will slowly increase or become unstable with time.
The thermal impedance, when measured during this time may appear to
decrease or change erratically.
The mechanical stresses from the application of power can also propagate
fractures in the silicon when the die is thermally mismatched to the solder/heat
sink system. These fractures will manifest themselves in the form of shorted
gates or degraded breakdown characteristics (
V
(BR)CES
).
IGBT / CoPack
Quarterly Reliability Report
Page 28 of 35
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