參數(shù)資料
型號： IS42S32800B-7BL
廠商： INTEGRATED SILICON SOLUTION INC
元件分類： DRAM
英文描述： 2M Words x 32 Bits x 4 Banks (256-MBIT) SYNCHRONOUS DYNAMIC RAM
中文描述： 8M X 32 SYNCHRONOUS DRAM, 5.5 ns, PBGA90
封裝： 8 X 13 MM, 0.80 MM PITCH, LEAD FREE, MO-207, BGA-90
文件頁數(shù)： 12/62頁
文件大?。?/td> 939K
代理商： IS42S32800B-7BL
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev.
B
0
5/24
/06
ISSI
IS42S32800B
CLK
COMMAND
DIN B2
NOP
WRITEA
WRITEB
NOP
NOP
NOP
NOP
NOP
NOP
DIN A0
DIN B0
DIN B1
DQ’s
DIN B3
1 Clk Interval
T0
T2
T1
T3
T4
T5
T6
T7
T8
CLK
COMMAND
T0
T 1
T2
T3
T4
T5
T6
T7
T8
NOP
WRITEA
NOP
NOP
NOP
NOP
NOP
READ B
NOP
DIN A0
don’t care
DOUT B2
DOUT B0
DOUT B1
DOUT B3
DIN A0
don’t care
don’t care
DOUT B2
DOUT B0
DOUT B1
DOUT B3
DIN
Input data must be removed from the DQs at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.
Input data for the write is masked.
CAS# latency=2
tCK2, DQ’s
CAS# latency=3
tCK3, DQ’s
CLK
WRITE
COMMAND
BANK (S)
ROW
NOP
NOP
Precharge
NOP
NOP
Activate
BANK
COL n
DIN
n
n + 1
DQM
ADDRESS
DQ
tWR
tRP
: dont care
T0
T2
T1
T3
T4
T5
T6
Write Interrupted by a Write (Burst Length =4,CAS#Latency =2,3)
The Read command that interrupts a write burst without auto precharge function should be issued one cycle after
the clock edge in which the last data-in element is registered.In order to avoid data contention,input data must
be removed from the DQs at least one clock cycle before the first read data appears on the outputs (refer to the
following figure).Once the Read command is registered,the data inputs will be ignored and writes will not be
executed.
Write Interrupted by a Read (Burst Length =4,CAS#Latency =2,3)
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto precharge function
should be issued
m
cycles after the clock edge in which the last data-in element is registered,where
m
equals tWR/
tCK rounded up to the next whole number.In addition,the DQM signals must be used to mask input data,starting
with the clock edge following the last data-in element and ending with the clock edge on which the BankPrecharge/
PrechargeAll command is entered (refer to the following figure).
Note:
The DQMs can remain low in this example if the length of the write burst is 1 or 2.
Write to Precharge
相關(guān)PDF資料
PDF描述
IS42S32800B-7BLI 2M Words x 32 Bits x 4 Banks (256-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42S32800B-7T 2M Words x 32 Bits x 4 Banks (256-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42S32800B-7TI 2M Words x 32 Bits x 4 Banks (256-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42S32800B-7TL 2M Words x 32 Bits x 4 Banks (256-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42S32800B-7TLI 2M Words x 32 Bits x 4 Banks (256-MBIT) SYNCHRONOUS DYNAMIC RAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IS42S32800B-7BLI 功能描述:動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器 256M 8Mx32 143Mhz RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲(chǔ)容量:16 MB 最大時(shí)鐘頻率: 訪問時(shí)間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube
IS42S32800B-7BLI-TR 功能描述:動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器 256M 8Mx32 143Mhz RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲(chǔ)容量:16 MB 最大時(shí)鐘頻率: 訪問時(shí)間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube
IS42S32800B-7BL-TR 功能描述:動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器 256M 8Mx32 143Mhz RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲(chǔ)容量:16 MB 最大時(shí)鐘頻率: 訪問時(shí)間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube
IS42S32800B-7B-TR 功能描述:動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器 256M 8Mx32 143Mhz RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲(chǔ)容量:16 MB 最大時(shí)鐘頻率: 訪問時(shí)間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube
IS42S32800B-7T 功能描述:動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器 256M 8Mx32 143Mhz RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲(chǔ)容量:16 MB 最大時(shí)鐘頻率: 訪問時(shí)間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube
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