參數(shù)資料
型號(hào): IS42S32800B-7BL
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 2M Words x 32 Bits x 4 Banks (256-MBIT) SYNCHRONOUS DYNAMIC RAM
中文描述: 8M X 32 SYNCHRONOUS DRAM, 5.5 ns, PBGA90
封裝: 8 X 13 MM, 0.80 MM PITCH, LEAD FREE, MO-207, BGA-90
文件頁(yè)數(shù): 8/62頁(yè)
文件大?。?/td> 939K
代理商: IS42S32800B-7BL
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev.
B
0
5/24
/06
ISSI
IS42S32800B
3
PrechargeAll command
(RAS#=”L”,CAS#=”H”,WE#=”L”,BS =Don t care,A10 =”H”)
The Precharge
All command precharges all the four banks simultaneously and can be issued even if all banks are
not in the active state.
All banks are then switched to the idle state.
4
Read command
(RAS#=”H”,CAS#=”L”,WE#=”H”,BS =Bank,A10 =”L”,A0-A7 =Column Address)
The Read command is used to read a burst of data on consecutive clock cycles from an active row in an active
bank.The bank must be active for at least tRCD(min.)
before the Read command is issued.During read bursts,
the valid data-out element from the starting column address will be available following the CAS#
latency after the
issue of the Read command.Each subsequent data- out element will be valid by the next positive clock edge (refer
to the following figure).The DQs go into high-impedance at the end of the burst unless other command is initiated.
The burst length,burst sequence,and CAS#
latency are determined by the mode register which is already
programmed.A full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and
continue).
相關(guān)PDF資料
PDF描述
IS42S32800B-7BLI 2M Words x 32 Bits x 4 Banks (256-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42S32800B-7T 2M Words x 32 Bits x 4 Banks (256-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42S32800B-7TI 2M Words x 32 Bits x 4 Banks (256-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42S32800B-7TL 2M Words x 32 Bits x 4 Banks (256-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42S32800B-7TLI 2M Words x 32 Bits x 4 Banks (256-MBIT) SYNCHRONOUS DYNAMIC RAM
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