參數(shù)資料
型號： IS42VS16100C1-10T
廠商： INTEGRATED SILICON SOLUTION INC
元件分類： DRAM
英文描述： 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
中文描述： 1M X 16 SYNCHRONOUS DRAM, 7 ns, PDSO50
封裝： 0.400 INCH, PLASTIC, MS-24, TSOP2-50
文件頁數(shù)： 12/80頁
文件大?。?/td> 772K
代理商： IS42VS16100C1-10T
IS42VS16100C1
ISSI
12
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00A
04/15/05
Mode Register Set Command
(
CS
,
RAS
,
CAS
,
WE
= LOW)
The IS42VS16100C1 product incorporates a register that
defines the device operating mode. This command
functions as a data input pin that loads this register from
the pins A0 to A11. When power is first applied, the
stipulated power-on sequence should be executed and
then the IS42VS16100C1 should be initialized by executing
a mode register set command.
Note that the mode register set command can be executed
only when both banks are in the idle state (i.e. deactivated).
Another command cannot be executed after a mode
register set command until after the passage of the period
t
MCD
, which is the period required for mode register set
command execution.
Active Command
(
CS
,
RAS
= LOW,
CAS
,
WE
= HIGH)
The IS42VS16100C1 includes two banks of 2048 rows
each. This command selects one of the two banks
according to the A11 pin and activates the row selected by
the pins A0 to A10.
This command corresponds to the fall of the
RAS
signal
from HIGH to LOW in conventional DRAMs.
Precharge Command
(
CS
,
RAS
,
WE
= LOW,
CAS
= HIGH)
This command starts precharging the bank selected by
pins A10 and A11. When A10 is HIGH, both banks are
precharged at the same time. When A10 is LOW, the bank
selected by A11 is precharged. After executing this
command, the next command for the selected bank(s) is
executed after passage of the period t
RP
, which is the
period required for bank precharging.
This command corresponds to the
RAS
signal from LOW
to HIGH in conventional DRAMs
Read Command
(
CS
,
CAS
= LOW,
RAS
,
WE
= HIGH)
This command selects the bank specified by the A11 pin
and starts a burst read operation at the start address
specified by pins A0 to A9. Data is output following
CAS
latency.
The selected bank must be activated before executing
this command.
When the A10 pin is HIGH, this command functions as a
read with auto-precharge command. After the burst read
completes, the bank selected by pin A11 is precharged.
When the A10 pin is LOW, the bank selected by the A11 pin
remains in the activated state after the burst read completes.
Write Command
(
CS
,
CAS
,
WE
= LOW,
RAS
= HIGH)
When burst write mode has been selected with the mode
register set command, this command selects the bank
specified by the A11 pin and starts a burst write operation
at the start address specified by pins A0 to A9. This first
data must be input to the DQ pins in the cycle in which this
command.
The selected bank must be activated before executing this
command.
When A10 pin is HIGH, this command functions as a write
with auto-precharge command. After the burst write
completes, the bank selected by pin A11 is precharged.
When the A10 pin is low, the bank selected by the A11 pin
remains in the activated state after the burst write completes.
After the input of the last burst write data, the application
must wait for the write recovery period (t
DPL
, t
DAL
) to elapse
according to
CAS
latency.
Auto-Refresh Command
(
CS
,
RAS
,
CAS
= LOW,
WE
, CKE = HIGH)
This command executes the auto-refresh operation. The
row address and bank to be refreshed are automatically
generated during this operation.
Both banks must be placed in the idle state before executing
this command.
The stipulated period (t
RC
) is required for a single refresh
operation, and no other commands can be executed during
this period.
The device goes to the idle state after the internal refresh
operation completes.
This command must be executed at least 2048 times every
32 ms.
This command corresponds to CBR auto-refresh in
conventional DRAMs.
相關(guān)PDF資料
PDF描述
IS42VS16100C1-10TI 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42VS16100C1-10TL 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42VS16400C1 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42VS16400C1-10T 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42VS16400C1-10TL 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IS42VS16100C1-10TI 功能描述:動態(tài)隨機(jī)存取存儲器 16M 1.8V 1Mx16 100Mhz RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲容量:16 MB 最大時鐘頻率: 訪問時間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube
IS42VS16100C1-10TI-TR 功能描述:動態(tài)隨機(jī)存取存儲器 16M 1.8V 1Mx16 100Mhz RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲容量:16 MB 最大時鐘頻率: 訪問時間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube
IS42VS16100C1-10TL 功能描述:動態(tài)隨機(jī)存取存儲器 16M 1.8V 1Mx16 100Mhz RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲容量:16 MB 最大時鐘頻率: 訪問時間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube
IS42VS16100C1-10TLI 功能描述:動態(tài)隨機(jī)存取存儲器 16M 1.8V 1Mx16 100Mhz RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲容量:16 MB 最大時鐘頻率: 訪問時間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube
IS42VS16100C1-10TLI-TR 功能描述:動態(tài)隨機(jī)存取存儲器 16M 1.8V 1Mx16 100Mhz RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲容量:16 MB 最大時鐘頻率: 訪問時間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube
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