參數(shù)資料
型號: IS42VS16100C1-10T
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
中文描述: 1M X 16 SYNCHRONOUS DRAM, 7 ns, PDSO50
封裝: 0.400 INCH, PLASTIC, MS-24, TSOP2-50
文件頁數(shù): 31/80頁
文件大小: 772K
代理商: IS42VS16100C1-10T
IS42VS16100C1
ISSI
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00A
04/15/05
31
Precharge
The precharge command sets the bank selected by pin A11
to the precharged state. This command can be executed at
a time t
RAS
following the execution of an active command to
the same bank. The selected bank goes to the idle state at
a time t
RP
following the execution of the precharge command,
and an active command can be executed again for that
bank.
If pin A10 is low when this command is executed, the bank
selected by pin A11 will be precharged, and if pin A10 is
HIGH, both banks will be precharged at the same time. This
input to pin A11 is ignored in the latter case.
Read Cycle Interruption
Using the Precharge Command
A read cycle can be interrupted by the execution of the
precharge command before that cycle completes. The
delay time (t
RQL
) from the execution of the precharge
command to the completion of the burst output is the
clock cycle of
CAS
latency.
CAS
Latency
t
RQL
3
3
2
2
t
RQL
t
RQL
PRE 0
READ A0
COMMAND
DQ
CLK
D
OUT
A0
D
OUT
A1
D
OUT
A2
HI-Z
READ (CA=A, BANK 0)
PRECHARGE (BANK 0)
PRE 0
READ A0
COMMAND
DQ
CLK
D
OUT
A0
D
OUT
A1
D
OUT
A2
HI-Z
READ (CA=A, BANK 0)
PRECHARGE (BANK 0)
CAS
latency = 2, burstlength = 4
CAS
latency = 3, burstlength = 4
相關PDF資料
PDF描述
IS42VS16100C1-10TI 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42VS16100C1-10TL 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42VS16400C1 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42VS16400C1-10T 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42VS16400C1-10TL 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
相關代理商/技術參數(shù)
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