參數(shù)資料
型號: IS42VS16100C1-10TI
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
中文描述: 1M X 16 SYNCHRONOUS DRAM, 7 ns, PDSO50
封裝: 0.400 INCH, PLASTIC, MS-24, TSOP2-50
文件頁數(shù): 33/80頁
文件大?。?/td> 772K
代理商: IS42VS16100C1-10TI
IS42VS16100C1
ISSI
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00A
04/15/05
33
Read Cycle (Full Page) Interruption Using
the Burst Stop Command
The IS42VS16100C1 can output data continuously from
the burst start address (a) to location a+255 during a read
cycle in which the burst length is set to full page. The
IS42VS16100C1 repeats the operation starting at the 256th
cycle with the data output returning to location (a) and
continuing with a+1, a+2, a+3, etc. A burst stop command
must be executed to terminate this cycle. A precharge
command must be executed within the ACT to PRE
command period (t
RAS
max.) following the burst stop
command.
After the period (t
RBD
) required for burst data output to
stop following the execution of the burst stop command
has elapsed, the outputs go to the HIGH impedance
state. This period (t
RBD
) is two clock cycle when the
CAS
latency is two and three clock cycle when the
CAS
latency is three.
CAS
Latency
t
RBD
3
3
2
2
BST
READ A0
COMMAND
DQ
CLK
t
RBD
READ (CA=A, BANK 0)
BURST STOP
HI-Z
D
OUT
A0
D
OUT
A0
D
OUT
A1
D
OUT
A2
COMMAND
DQ
CLK
t
RBD
READ A0
READ (CA=A, BANK 0)
BURST STOP
BST
HI-Z
D
OUT
A0
D
OUT
A0
D
OUT
A1
D
OUT
A2
D
OUT
A3
D
OUT
A3
CAS
latency = 3, burstlength = 4
CAS
latency = 2, burstlength = 4
相關PDF資料
PDF描述
IS42VS16100C1-10TL 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42VS16400C1 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42VS16400C1-10T 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42VS16400C1-10TL 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42VS16400C1-10TLI 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
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