參數(shù)資料
型號(hào): IS42VS16100C1-10TL
廠商: INTEGRATED SILICON SOLUTION INC
元件分類(lèi): DRAM
英文描述: 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
中文描述: 1M X 16 SYNCHRONOUS DRAM, 7 ns, PDSO50
封裝: 0.400 INCH, LEAD FREE, PLASTIC, MS-24, TSOP2-50
文件頁(yè)數(shù): 36/80頁(yè)
文件大小: 772K
代理商: IS42VS16100C1-10TL
IS42VS16100C1
ISSI
36
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00A
04/15/05
Bank Active Command Interval
When the selected bank is precharged, the period trp
has elapsed and the bank has entered the idle state, the
bank can be activated by executing the active
command. If the other bank is in the idle state at that
time, the active command can be executed for that bank
after the period t
RRD
has elapsed. At that point both
banks will be in the active state. When a bank active
command has been executed, a precharge command
must be executed for
that bank within the ACT to PRE command period (t
RAS
max). Also note that a precharge command cannot be
executed for an active bank before t
RAS
(min) has elapsed.
After a bank active command has been executed and the
trcd period has elapsed, read write (including auto-precharge)
commands can be executed for that bank.
ACT 0
ACT 1
COMMAND
CLK
BANK ACTIVE (BANK 0)
BANK ACTIVE (BANK 1)
t
RRD
ACT 0
READ 0
COMMAND
CLK
BANK ACTIVE (BANK 0)
BANK ACTIVE (BANK 0)
t
RCD
CAS
latency = 3
Clock Suspend
When the CKE pin is dropped from HIGH to LOW during a
read or write cycle, the IS42VS16100C1 enters clock
suspend mode on the next CLK rising edge. This command
reduces the device power dissipation by stopping the
device internal clock. Clock suspend mode continues as
long as the CKE pin remains low. In this state, all inputs
other than CKE pin are invalid and no other commands can
be executed. Also, the device internal states are maintained.
When the CKE pin goes from LOW to HIGH clock suspend
mode is terminated on the next CLK rising edge and device
operation resumes.
The next command cannot be executed until the recovery
period (t
CKA
) has elapsed.
Since this command differs from the self-refresh command
described previously in that the refresh operation is not
performed automatically internally, the refresh operation
must be performed within the refresh period (tref). Thus the
maximum time that clock suspend mode can be held is just
under the refresh cycle time.
READ 0
COMMAND
CKE
DQ
CLK
D
OUT
0
D
OUT
1
D
OUT
2
D
OUT
3
READ (BANK 0)
CLOCK SUSPEND
CAS
latency = 2, burstlength = 4
相關(guān)PDF資料
PDF描述
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IS42VS16400C1-10TL 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
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