參數(shù)資料
型號(hào): IS42VS16100C1-10TL
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
中文描述: 1M X 16 SYNCHRONOUS DRAM, 7 ns, PDSO50
封裝: 0.400 INCH, LEAD FREE, PLASTIC, MS-24, TSOP2-50
文件頁數(shù): 7/80頁
文件大?。?/td> 772K
代理商: IS42VS16100C1-10TL
IS42VS16100C1
ISSI
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00A
04/15/05
7
AC CHARACTERISTICS
(1,2,3)
-10
Symbol Parameter
Min.
Max.
Units
t
CK
3
t
CK
2
Clock Cycle Time
CAS
Latency = 3
CAS
Latency = 2
10
12
ns
ns
t
AC
3
t
AC
2
Access Time From CLK
(4)
CAS
Latency = 3
CAS
Latency = 2
7
8
ns
ns
t
CHI
CLK HIGH Level Width
3
ns
t
CL
CLK LOW Level Width
3
ns
t
OH
3
t
OH
2
Output Data Hold Time
CAS
Latency = 3
CAS
Latency = 2
2
2
ns
ns
t
LZ
Output LOW Impedance Time
0
ns
t
HZ
3
t
HZ
2
Output HIGH Impedance Time
(5)
CAS
Latency = 3
CAS
Latency = 2
7
8
ns
ns
t
DS
Input Data Setup Time
2
ns
t
DH
Input Data Hold Time
1
ns
t
AS
Address Setup Time
2
ns
t
AH
Address Hold Time
1
ns
t
CKS
CKE Setup Time
2.5
ns
t
CKH
CKE Hold Time
1
ns
t
CKA
CKE to CLK Recovery Delay Time
1CLK+3
ns
t
CS
Command Setup Time (
CS
,
RAS
,
CAS
,
WE
, DQM)
2
ns
t
CH
Command Hold Time (
CS
,
RAS
,
CAS
,
WE
, DQM)
1
ns
t
RC
Command Period (REF to REF / ACT to ACT)
94
ns
t
RAS
Command Period (ACT to PRE)
50
100,000
ns
t
RP
Command Period (PRE to ACT)
24
ns
t
RCD
Active Command To Read / Write Command Delay Time
24
ns
t
RRD
Command Period (ACT [0] to ACT[1])
18
ns
t
DPL
3
Input Data To Precharge
Command Delay time
CAS
Latency = 3
2CLK
ns
t
DPL
2
CAS
Latency = 2
2CLK
ns
t
DAL
3
Input Data To Active / Refresh
Command Delay time (During Auto-Precharge)
CAS
Latency = 3
2CLK+t
RP
ns
t
DAL
2
CAS
Latency = 2
2CLK+t
RP
ns
t
T
Transition Time
0.5
5
ns
t
REF
Refresh Cycle Time (2048)
32
ms
Notes:
1. Thepower-on sequence must be executed before starting memory operation.
2. Measured with t
T
= 0.5 ns.
3. The reference level is 0.9V when measuring input signal timing. Rise and fall times are measured between V
IH
(min.) and V
IL
(max.).
4. Access time is measured at 0.9V with the load shown in the figure below.
5. The time t
HZ
(max.) is defined as the time required for the output voltage to become high impedance.
相關(guān)PDF資料
PDF描述
IS42VS16400C1 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42VS16400C1-10T 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42VS16400C1-10TL 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42VS16400C1-10TLI 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42VS16400C1-12T 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
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