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參數(shù)資料
| 型號(hào)： | IS42VS16400C1-10T |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| 中文描述： | 4M X 16 SYNCHRONOUS DRAM, 8 ns, PDSO54 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP2-54 |
| 文件頁(yè)數(shù)： | 15/56頁(yè) |
| 文件大?。?/td> | 509K |
| 代理商： | IS42VS16400C1-10T |
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IS42VS16400C1
ISSI
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
10/06/05
15
OPERATING FREQUENCY / LATENCY RELATIONSHIPS
SYMBOL PARAMETER
—
Clock Cycle Time
—
Operating Frequency
-10
10
100
-10
12
83
-12
12
83
-12
15
66
UNITS
ns
MHz
t
CAC
t
RCD
t
RAC
CAS
Latency
Active Command To Read/Write Command Delay Time
RAS
Latency (t
RCD
+ t
CAC
)
3
3
6
—
10
5
3
2
1
2/3
3
6
5
8
5
3
2
1
3
3
6
—
8
3
3
2
1
2/3
2
5
4
7
2
2
2
1
cycle
cycle
cycle
CAS
Latency = 3
CAS
Latency = 2
t
RC
t
RAS
t
RP
t
RRD
t
CCD
Command Period (REF to REF / ACT to ACT)
Command Period (ACT to PRE)
Command Period (PRE to ACT)
Command Period (ACT[0] to ACT [1])
Column Command Delay Time
(READ, READA, WRIT, WRITA)
Input Data To Precharge Command Delay Time
Input Data To Active/Refresh Command Delay Time
(During Auto-Precharge)
Burst Stop Command To Output in HIGH-Z Delay Time
CAS
Latency = 3
(Read)
Burst Stop Command To Input in Invalid Delay Time
(Write)
Precharge Command To Output in HIGH-Z Delay Time
CAS
Latency = 3
(Read)
Precharge Command To Input in Invalid Delay Time
(Write)
Last Output To Auto-Precharge Start Time (Read)
cycle
cycle
cycle
cycle
cycle
t
DPL
t
DAL
2
5
2
5
2
5
2
4
cycle
cycle
t
RBD
3
—
0
3
2
0
3
—
0
3
2
0
cycle
CAS
Latency = 2
t
WBD
cycle
t
RQL
3
—
0
3
2
0
3
—
0
3
2
0
cycle
CAS
Latency = 2
t
WDL
cycle
t
PQL
CAS
Latency = 3
CAS
Latency = 2
-2
—
2
0
2
-2
-1
2
0
2
-2
—
2
0
2
-2
-1
2
0
2
cycle
t
QMD
t
DMD
t
MRD
DQM To Output Delay Time (Read)
DQM To Input Delay Time (Write)
Mode Register Set To Command Delay Time
cycle
cycle
cycle
AC TEST CONDITIONS
(Input/Output Reference Level: 0.9V)
Input
I/O
50
0.5 x VDDQ V
30 pF
Output Load
t
OH
t
AC
0.9V
0.9V
t
CH
t
CS
t
CK
t
CHI
t
CL
1.8V
0.9V
0.0V
1.8V
0.9V
0.0V
CLK
INPUT
OUTPUT
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IS42VS16400C1-10TL | 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42VS16400C1-10TLI | 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42VS16400C1-12T | 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42VS16400C1-12TI | 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42VS16400C1-12TL | 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS42VS16400C1-10TL | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42VS16400C1-10TLI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42VS16400C1-12T | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42VS16400C1-12TI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42VS16400C1-12TL | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
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