參數(shù)資料
型號(hào)： IS42VS16400C1-10T
廠商： INTEGRATED SILICON SOLUTION INC
元件分類： DRAM
英文描述： 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
中文描述： 4M X 16 SYNCHRONOUS DRAM, 8 ns, PDSO54
封裝： 0.400 INCH, PLASTIC, TSOP2-54
文件頁數(shù)： 16/56頁
文件大小： 509K
代理商： IS42VS16400C1-10T
IS42VS16400C1
ISSI
16
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
10/06/05
FUNCTIONAL DESCRIPTION
The 64Mb SDRAMs (1 Meg x 16 x 4 banks) are quad-bank
DRAMs which operate at 1.8V and include a synchronous
interface (all signals are registered on the positive edge of
the clock signal, CLK). Each of the 16,777,216-bit banks
is organized as 4,096 rows by 256 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a
programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed
(BA0 and BA1 select the bank, A0-A11
select the row)
. The address bits
(A0-A7)
registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.
Prior to normal operation, the SDRAM must be initialized.
The following sections provide detailed information covering
device initialization, register definition, command
descriptions and device operation.
Initialization
SDRAMs must be powered up and initialized in a
predefined manner.
The 64M SDRAM is initialized after the power is applied
to V
DD
and V
DDQ
(simultaneously), and the clock is stable
with DQM High and CKE High.
A 100μs delay is required prior to issuing any command
other than a
COMMAND INHIBIT
or a
NOP
. The COMMAND
INHIBIT or NOP may be applied during the 100μs period and
continue should at least through the end of the period.
With at least one COMMAND INHIBIT or NOP command
having been applied, a PRECHARGE command should be
applied once the 100μs delay has been satisfied. All banks
must be precharged. This will leave all banks in an idle
state,
after which at least two AUTO REFRESH
cycles must
be performed. After the
AUTO REFRESH
cycles are com-
plete, the SDRAM is then ready for mode register program-
ming.
The mode register should be loaded prior to applying any
operational command because it will power up in an
unknown state. After the Load Mode Register command, at
least two NOP commands must be asserted prior to any
command.
相關(guān)PDF資料
PDF描述
IS42VS16400C1-10TL 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42VS16400C1-10TLI 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42VS16400C1-12T 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42VS16400C1-12TI 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42VS16400C1-12TL 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IS42VS16400C1-10TL 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42VS16400C1-10TLI 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42VS16400C1-12T 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42VS16400C1-12TI 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42VS16400C1-12TL 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
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