參數(shù)資料
型號: IS43R16160A-5T
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 16Meg x 16 256-MBIT DDR SDRAM
中文描述: 16M X 16 DDR DRAM, 0.65 ns, PDSO66
封裝: PLASTIC, TSOP2-66
文件頁數(shù): 32/56頁
文件大?。?/td> 792K
代理商: IS43R16160A-5T
32
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00B
11/28/05
ISSI
IS43R16160A
AC Operating Conditions & Timing Specification
AC Operating Conditions
Note:
1.Vih(max) = 4.2V. The overshoot voltage duration is < 3ns at VDD.
2. Vil(min) = -1.5V. The undershoot voltage duration is < 3ns at VSS.
3. VID is the magnitude of the difference between the input level on CK and the input on CK.
4. The value of V
IX
is expected to equal 0.5*V
DDQ
of the transmitting device and must track variations in the DC level of the same.
ELECTRICAL CHARACTERISTICS AND AC TIMING for PC400/PC333/PC266 -Absolute Spec-
ifications
(Notes: 1-5, 14-17) (0°C < T
A
< 70°C; V
DDQ
= +2.5V ±0.2V, V
DD
=+2.5V ±0.2V for DDR400 device V
DDQ
= +2.6V ±0.1V,
V
DD
=+2.6V ±0.1V)
Parameter/Condition
Symbol
Min
Max
Unit
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
VIH(AC)
VREF + 0.31
V
1
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
VIL(AC)
VREF - 0.31
V
2
Input Differential Voltage, CK and CK inputs
VID(AC)
0.7
VDDQ+0.6
V
3
Input Crossing Point Voltage, CK and CK inputs
VIX(AC)
0.5*VDDQ-0.2
0.5*VDDQ+0.2
V
4
AC CHARACTERISTICS
-5
-6
PARAMETER
SYM-
BOL
MIN
MAX
MIN
MAX
UNITS
NOTES
Access window of DQs from CK/CK
t
AC
-0.65
0.65
-0.7
0.7
ns
CK high-level width
t
CH
0.45
0.55
0.45
0.55
t
CK
30
CK low-level width
t
CL
0.45
5
10
6
12
0.55
0.45
0.55
t
CK
30
Clock cycle time
CL = 3
(3)
t
CK
ns
52
CL = 2.5
t
CK (2.5)
6
10
6
12
ns
52
CL = 2
t
CK (2)
7.5
10
7.5
12
ns
52
DQ and DM input hold time relative to
DQS
t
DH
0.40
0.45
ns
26,31
DQ and DM input setup time relative to
DQS
t
DS
0.40
0.45
ns
26,31
DQ and DM input pulse width (for each in-
put)
t
DIPW
1.75
1.75
ns
31
Access window of DQS from CK/CK
t
DQSCK
-0.6
0.6
-0.6
0.6
ns
DQS input high pulse width
t
DQSH
0.35
0.35
t
CK
DQS input low pulse width
t
DQSL
0.35
0.35
t
CK
DQS-DQ skew, DQS to last DQ valid,
per group, per access
t
DQSQ
0.40
0.45
ns
25,26
Write command to first DQS latching tran-
sition
t
DQSS
0.72
1.25
0.75
1.25
t
CK
DQS falling edge to CK rising - setup time
t
DSS
0.2
0.2
t
CK
DQS falling edge from CK rising - hold
time
t
DSH
0.2
0.2
t
CK
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