參數(shù)資料
型號: IS45S81600B-7TLA1
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM
中文描述: 16M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
封裝: LEAD FREE, PLASTIC, TSOP2-54
文件頁數(shù): 17/59頁
文件大?。?/td> 593K
代理商: IS45S81600B-7TLA1
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
04/14/06
17
ISSI
IS45S81600B, IS45S16800B
OPERATING FREQUENCY / LATENCY RELATIONSHIPS
SYMBOL
PARAMETER
UNITS
Clock Cycle Time
7
10
ns
Operating Frequency
(
CAS
Latency = 3)
143
100
MHz
t
CAC
CAS
Latency
3
2/3
cycle
t
RCD
Active Command To Read/Write Command Delay Time
3
2
cycle
t
RAC
RAS
Latency (t
RCD
+ t
CAC
)
CAS
Latency = 3
CAS
Latency = 2
6
5
4
cycle
t
RC
Command Period (REF to REF / ACT to ACT)
10
7
cycle
t
RAS
Command Period (ACT to PRE)
7
5
cycle
t
RP
Command Period (PRE to ACT)
3
2
cycle
t
RRD
Command Period (ACT[0] to ACT [1])
2
2
cycle
t
CCD
Column Command Delay Time
(READ, READA, WRIT, WRITA)
1
1
cycle
t
DPL
Input Data To Precharge Command Delay Time
2
2
cycle
t
DAL
Input Data To Active/Refresh Command Delay Time
(During Auto-Precharge)
5
4
cycle
t
RBD
Burst Stop Command To Output in HIGH-Z Delay Time
CAS
Latency = 3
(Read)
3
3
2
cycle
CAS
Latency = 2
t
WBD
Burst Stop Command To Input in Invalid Delay Time
(Write)
0
0
cycle
t
RQL
Precharge Command To Output in HIGH-Z Delay Time
CAS
Latency = 3
(Read)
3
3
2
cycle
CAS
Latency = 2
t
WDL
Precharge Command To Input in Invalid Delay Time
(Write)
0
0
cycle
t
PQL
Last Output To Auto-Precharge Start Time (Read)
CAS
Latency = 3
CAS
Latency = 2
–2
-2
-1
cycle
t
QMD
DQM To Output Delay Time (Read)
2
2
cycle
t
DMD
DQM To Input Delay Time (Write)
0
0
cycle
t
MRD
Mode Register Set To Command Delay Time
2
2
cycle
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