參數(shù)資料
型號(hào)： IS45S81600B-7TLA1
廠商： INTEGRATED SILICON SOLUTION INC
元件分類： DRAM
英文描述： 16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM
中文描述： 16M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
封裝： LEAD FREE, PLASTIC, TSOP2-54
文件頁數(shù)： 24/59頁
文件大?。?/td> 593K
代理商： IS45S81600B-7TLA1
ISSI
24
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
04/14/06
IS45S81600B, IS45S16800B
BURST DEFINITION
Burst
Starting Column
Order of Accesses Within a Burst
Length
Address
Type = Sequential
Type = Interleaved
A 0
2
0
0-1
0-1
1
1-0
1-0
A 1
A 0
0
0
0-1-2-3
0-1-2-3
4
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
2-3-0-1
1
1
3-0-1-2
3-2-1-0
A 2
A 1
A 0
0
0
0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
8
0
1
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
Full
Page
(y)
n = A0-A7
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
…Cn - 1,
Cn…
Not Supported
(location 0-y)
BURST LENGTH
Read and write accesses to the SDRAM are burst oriented,
with the burst length being programmable, as shown in
MODE REGISTER DEFINITION. The burst length deter-
mines the maximum number of column locations that can
be accessed for a given READ or WRITE command. Burst
lengths of 1, 2, 4 or 8 locations are available for both the
sequential and the interleaved burst types, and a full-page
burst is available for the sequential type. The full-page burst
is used in conjunction with the BURST TERMINATE com-
mand to generate arbitrary burst lengths.
Reserved states should not be used, as unknown operation
or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, mean-
ing that the burst will wrap within the block if a boundary is
reached. The block is uniquely selected by A1-A8 (x16)
when the burst length is set to two; by A2-A8 (x16) when the
burst length is set to four; and by A3-A8 (x16) when the burst
length is set to eight. The remaining (least significant)
address bit(s) is (are) used to select the starting location
within the block. Full-page bursts wrap within the page if the
boundary is reached.
Burst Type
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the
burst length, the burst type and the starting column address,
as shown in BURST DEFINITION table.
相關(guān)PDF資料
PDF描述
IS45S32200C1 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS45S32200C1-7BLA1 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS45S32200C1-7TA1 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS45S32200C1-7TLA 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS45S32200C1-7TLA1 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IS45S81600E 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:16M x 8, 8M x16 128Mb SYNCHRONOUS DRAM
IS45S81600E-6TLA1 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:16M x 8, 8M x16 128Mb SYNCHRONOUS DRAM
IS45S81600E-7CTNA1 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:16M x 8, 8M x16 128Mb SYNCHRONOUS DRAM
IS45S81600E-7CTNA2 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:16M x 8, 8M x16 128Mb SYNCHRONOUS DRAM
IS45S81600E-7TLA1 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:16M x 8, 8M x16 128Mb SYNCHRONOUS DRAM
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*