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| 型號(hào)： | IS61LPS51218A-250B2I |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM |
| 中文描述： | 512K X 18 CACHE SRAM, 2.6 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-119 |
| 文件頁(yè)數(shù)： | 10/32頁(yè) |
| 文件大?。?/td> | 217K |
| 代理商： | IS61LPS51218A-250B2I |
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10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/29/05
IS61VPS25636A, IS61LPS25636A, IS61VPS51218A, IS61LPS51218A
ISSI
PARTIAL TRUTH TABLE
Function
Read
Read
Write Byte 1
Write All Bytes
Write All Bytes
GW
H
H
H
H
L
BWE
H
L
L
L
X
BWa
X
H
L
L
X
BWb
X
H
H
L
X
BWc
X
H
H
L
X
BWd
X
H
H
L
X
TRUTH TABLE
(1-8)
OPERATION
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Snooze Mode, Power-Down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
NOTE:
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
2. For
WRITE
, L means one or more byte write enable signals (
BWa-d
) and
BWE
are LOW or
GW
is LOW.
WRITE
= H for all
BWx
,
BWE
,
GW
HIGH.
3.
BWa
enables WRITEs to DQa’s and DQPa.
BWb
enables WRITEs to DQb’s and DQPb.
BWc
enables WRITEs to DQc’s and
DQPc.
BWd
enables WRITEs to DQd’s and DQPd. DQPa and DQPb are available on the x18 version. DQPa-DQPd are
available on the x36 version.
4. All inputs except
OE
and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation,
OE
must be HIGH before the input data setup time and held HIGH during the
input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8.
ADSP
LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write
enable signals and
BWE
LOW or
GW
LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.
ADDRESS
None
None
None
None
None
None
External
External
External
External
External
Next
Next
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
CE
H
L
L
L
L
X
L
L
L
L
L
X
X
H
H
X
H
X
X
H
H
X
H
CE2
X
X
H
X
H
X
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
CE–2
X
L
X
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
ZZ
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
ADSP
X
L
L
H
H
X
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
ADSC ADV
L
X
X
L
L
X
X
X
L
L
L
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
H
H
H
H
WRITE
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
L
L
H
H
H
H
L
L
OE
X
X
X
X
X
X
L
H
X
L
H
L
H
L
H
X
X
L
H
L
H
X
X
CLK
L-H
L-H
L-H
L-H
L-H
X
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
DQ
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Q
High-Z
D
Q
High-Z
Q
High-Z
Q
High-Z
D
D
Q
High-Z
Q
High-Z
D
D
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS61LPS51218A-250B3 | 制造商:ISSI 制造商全稱(chēng):Integrated Silicon Solution, Inc 功能描述:256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM |
| IS61LPS51218A-250B3I | 制造商:ISSI 制造商全稱(chēng):Integrated Silicon Solution, Inc 功能描述:256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM |
| IS61LPS51218A-250TQ | 制造商:ISSI 制造商全稱(chēng):Integrated Silicon Solution, Inc 功能描述:256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM |
| IS61LPS51218A-250TQI | 制造商:ISSI 制造商全稱(chēng):Integrated Silicon Solution, Inc 功能描述:256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM |
| IS61LPS51218B-200TQLI | 功能描述:IC SRAM 9MBIT 200MHZ 100LQFP 制造商:issi, integrated silicon solution inc 系列:- 包裝:托盤(pán) 零件狀態(tài):在售 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類(lèi)型:SRAM - 同步 存儲(chǔ)容量:9M（512K x 18） 速度:200MHz 接口:并聯(lián) 電壓 - 電源:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C（TA） 封裝/外殼:100-LQFP 供應(yīng)商器件封裝:100-LQFP（14x20） 標(biāo)準(zhǔn)包裝:72 |
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