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參數(shù)資料
| 型號(hào)： | IS61LV12824-10B |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 128K x 24 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY |
| 中文描述： | 128K X 24 STANDARD SRAM, 10 ns, PBGA119 |
| 封裝： | PLASTIC, BGA-119 |
| 文件頁(yè)數(shù)： | 8/13頁(yè) |
| 文件大?。?/td> | 77K |
| 代理商： | IS61LV12824-10B |
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IS61LV12824
ISSI
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
06/22/05
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range)
-8
-10
Symbol
t
WC
t
SCE
t
SCE
2
t
AW
Parameter
Min.
Max.
Min.
Max.
Unit
Write Cycle Time
8
—
10
—
ns
CE1
,
CE2
to Write End
CE2 to Write End
7
7
—
—
8
8
—
—
ns
Address Setup Time
to Write End
7
—
8
—
ns
t
HA
t
SA
t
PWE
1
t
PWE
2
t
SD
t
HD
t
HZWE
(2)
t
LZWE
(2)
Address Hold from Write End
0
—
0
—
ns
Address Setup Time
0
—
0
—
ns
WE
Pulse Width (
OE
= HIGH)
6
—
8
—
ns
WE
Pulse Width (
OE
= LOW)
6
—
9
—
ns
Data Setup to Write End
4.5
—
5
—
ns
Data Hold from Write End
0
—
0
—
ns
WE
LOW to High-Z Output
—
3.5
—
3.5
ns
WE
HIGH to Low-Z Output
3
—
3
—
ns
Notes:
1. Test conditions assume signal transition times of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of
CE1
,
CE2
LOW, CE2 HIGH and
WE
LOW. All signals must be in valid
states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are
referenced to the rising or falling edge of the signal that terminates the write.
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PDF描述 |
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| IS61LV12824-10BI | 128K x 24 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY |
| IS61LV12824-10BL | 128K x 24 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY |
| IS61LV12824-10TQ | 128K x 24 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY |
| IS61LV12824-10TQI | 128K x 24 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY |
| IS61LV12824-10TQLI | 128K x 24 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS61LV12824-10BI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:128K x 24 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY |
| IS61LV12824-10BL | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 3Mb 128Kx24 10ns Async 靜態(tài)隨機(jī)存取存儲(chǔ)器 3.3v RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| IS61LV12824-10BL-TR | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 3Mb 128Kx24 10ns Async 靜態(tài)隨機(jī)存取存儲(chǔ)器 3.3v RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| IS61LV12824-10B-TR | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 3Mb 128Kx24 10ns Async 靜態(tài)隨機(jī)存取存儲(chǔ)器 3.3v RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| IS61LV12824-10TQ | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 3Mb 128Kx24 10ns Async 靜態(tài)隨機(jī)存取存儲(chǔ)器 3.3v RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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