參數(shù)資料
型號: IS61LV25616L-12TI
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY
中文描述: 256K X 16 STANDARD SRAM, 12 ns, PDSO44
封裝: TSOP2-44
文件頁數(shù): 7/11頁
文件大?。?/td> 74K
代理商: IS61LV25616L-12TI
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. B
06/28/02
7
1
2
3
4
5
6
7
8
9
10
11
12
IS61LV25616L
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range)
-10
-12
-15
Symbol
t
WC
t
SCE
t
AW
Parameter
Min. Max.
Min. Max.
Min. Max.
Unit
Write Cycle Time
10
12
15
ns
CE
to Write End
8
8
10
ns
Address Setup Time
to Write End
8
8
10
ns
t
HA
t
SA
t
PWB
t
PWE
1
t
PWE
2
t
SD
t
HD
t
HZWE
(2)
t
LZWE
(2)
Address Hold from Write End
0
0
0
ns
Address Setup Time
0
0
0
ns
LB
,
UB
Valid to End of Write
8
8
10
ns
WE
Pulse Width
8
8
10
ns
WE
Pulse Width (
OE
= LOW)
10
12
12
ns
Data Setup to Write End
6
6
7
ns
Data Hold from Write End
0
0
0
ns
WE
LOW to High-Z Output
5
6
7
ns
WE
HIGH to Low-Z Output
2
2
2
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of
CE
LOW and
UB
or
LB
, and
WE
LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
Shaded area product in development
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