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參數(shù)資料
| 型號： | IS65LV256AL-45UA3 |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 32K x 8 LOW VOLTAGE CMOS STATIC RAM |
| 中文描述： | 32K X 8 STANDARD SRAM, 45 ns, PDSO28 |
| 封裝： | 0.330 MM, PLASTIC, SOP-28 |
| 文件頁數(shù)： | 5/14頁 |
| 文件大?。?/td> | 113K |
| 代理商： | IS65LV256AL-45UA3 |
ISSI
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
03/17/06
5
IS65LV256AL
IS62LV256AL
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-20 ns
Min.
-45 ns
Min.
Symbol
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
(2)
t
HZOE
(2)
t
LZCE
(2)
t
HZCE
(2)
t
PU
(3)
t
PD
(3)
Parameter
Max.
Max.
Unit
Read Cycle Time
20
—
45
—
ns
Address Access Time
—
20
—
45
ns
Output Hold Time
2
—
2
—
ns
CE
Access Time
—
20
—
45
ns
OE
Access Time
—
10
—
25
ns
OE
to Low-Z Output
0
—
0
—
ns
OE
to High-Z Output
—
9
0
20
ns
CE
to Low-Z Output
3
—
3
—
ns
CE
to High-Z Output
—
9
0
20
ns
CE
to Power-Up
0
—
0
—
ns
CE
to Power-Down
—
18
—
30
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST LOADS
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1 and 2
Figure 1.
Figure 2.
635
Ω
30 pF
Including
jig and
scope
702
Ω
OUTPUT
3.3V
635
Ω
5 pF
Including
jig and
scope
702
Ω
OUTPUT
3.3V
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